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authorStephen Warren <swarren@nvidia.com>2013-11-07 17:58:21 (GMT)
committerStephen Warren <swarren@nvidia.com>2013-12-11 23:45:13 (GMT)
commita85f06badc3cff4069f2f5112cea63cd39d99920 (patch)
tree1f8550812bcf67687068b9e7e39459658ee02a0c /drivers
parent2ae77527bb1a510070d039aaa22d1ae9a5807b6f (diff)
downloadlinux-a85f06badc3cff4069f2f5112cea63cd39d99920.tar.xz
clk: tegra: remove bogus PCIE_XCLK
The "pcie_xclk" clock is not actually a clock at all, but rather a reset domain. Now that the custom Tegra module reset API has been removed, we can remove the definition of any "clocks" that existed solely to support it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/clk/tegra/clk-tegra20.c6
-rw-r--r--drivers/clk/tegra/clk-tegra30.c7
2 files changed, 0 insertions, 13 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 5a6a60d..dbace15 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -468,7 +468,6 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
{ .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
{ .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
- { .con_id = "pcie_xclk", .dt_id = TEGRA20_CLK_PCIE_XCLK },
{ .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
{ .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
{ .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
@@ -834,11 +833,6 @@ static void __init tegra20_periph_clk_init(void)
periph_clk_enb_refcnt);
clks[TEGRA20_CLK_PEX] = clk;
- /* pcie_xclk */
- clk = tegra_clk_register_periph_gate("pcie_xclk", "clk_m", 0, clk_base,
- 0, 74, periph_clk_enb_refcnt);
- clks[TEGRA20_CLK_PCIE_XCLK] = clk;
-
/* cdev1 */
clk = clk_register_fixed_rate(NULL, "cdev1_fixed", NULL, CLK_IS_ROOT,
26000000);
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 2e47383..8b10c38 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -649,7 +649,6 @@ static struct tegra_devclk devclks[] __initdata = {
{ .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
{ .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
{ .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
- { .con_id = "pciex", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIEX },
{ .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
{ .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
{ .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
@@ -1150,11 +1149,6 @@ static void __init tegra30_periph_clk_init(void)
periph_clk_enb_refcnt);
clks[TEGRA30_CLK_AFI] = clk;
- /* pciex */
- clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0,
- 74, periph_clk_enb_refcnt);
- clks[TEGRA30_CLK_PCIEX] = clk;
-
/* emc */
clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
ARRAY_SIZE(mux_pllmcp_clkm),
@@ -1395,7 +1389,6 @@ static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
- TEGRA_CLK_DUPLICATE(TEGRA30_CLK_PCIEX, "tegra_pcie", "pciex"),
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL), /* MUST be the last entry */
};