diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-05-05 14:17:31 (GMT) |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-05-21 20:57:57 (GMT) |
| commit | e3ef4479bb05dce255750ff10ec97c8675c0771b (patch) | |
| tree | 1f9a1ec51fbec01bc29af94f0dfac0e1dadf5d75 /drivers | |
| parent | adc289d749cf5b70bc5476045cc683f68898dba2 (diff) | |
| download | linux-e3ef4479bb05dce255750ff10ec97c8675c0771b.tar.xz | |
drm/i915: Fix DP enhanced framing for CPT
Currently we're always enabling enhanced framing on CPT even if the sink
doesn't support it. Fix this up by actaully looking at what the sink
tells us.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 9 |
2 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 268043f..52de411 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4168,8 +4168,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) temp &= ~(TRANS_DP_PORT_SEL_MASK | TRANS_DP_SYNC_MASK | TRANS_DP_BPC_MASK); - temp |= (TRANS_DP_OUTPUT_ENABLE | - TRANS_DP_ENH_FRAMING); + temp |= TRANS_DP_OUTPUT_ENABLE; temp |= bpc << 9; /* same format but at 11:9 */ if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 227e77e..d86e1f9 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1582,7 +1582,16 @@ static void intel_dp_prepare(struct intel_encoder *encoder) intel_dp->DP |= crtc->pipe << 29; } else if (HAS_PCH_CPT(dev) && port != PORT_A) { + u32 trans_dp; + intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; + + trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); + if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) + trans_dp |= TRANS_DP_ENH_FRAMING; + else + trans_dp &= ~TRANS_DP_ENH_FRAMING; + I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); } else { if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) intel_dp->DP |= intel_dp->color_range; |