diff options
| author | Ke Wei <kewei@marvell.com> | 2008-05-23 08:23:22 (GMT) |
|---|---|---|
| committer | Lennert Buytenhek <buytenh@marvell.com> | 2008-06-22 20:45:01 (GMT) |
| commit | 1219715de70956557b9dedf3ee021a73d4f4ec52 (patch) | |
| tree | 8d778c742bb7e5a0f087e8f8f88a210da6f0125a /include/asm-arm | |
| parent | ab6d15d50637fc25ee941710b23fed09ceb28db3 (diff) | |
| download | linux-1219715de70956557b9dedf3ee021a73d4f4ec52.tar.xz | |
[ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define
Some Feroceon-based SoCs have an MBUS bridge interrupt controller
that requires writing a one instead of a zero to clear edge
interrupt sources such as timer expiry.
This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform
code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or
BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'include/asm-arm')
| -rw-r--r-- | include/asm-arm/arch-orion5x/orion5x.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h index 20f7b40..10257f5 100644 --- a/include/asm-arm/arch-orion5x/orion5x.h +++ b/include/asm-arm/arch-orion5x/orion5x.h @@ -154,6 +154,7 @@ #define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) #define BRIDGE_INT_TIMER0 0x0002 #define BRIDGE_INT_TIMER1 0x0004 +#define BRIDGE_INT_TIMER1_CLR (~0x0004) #define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) #define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) |