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| author | Paul Mundt <lethal@linux-sh.org> | 2007-11-08 09:44:09 (GMT) |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2008-01-28 04:18:38 (GMT) |
| commit | 8d5fb297cc8f9f7de2840864e497bc38330abba6 (patch) | |
| tree | 61322fbbf95ce02923da6b568de559778cc59b18 /include/asm-sh/cpu-sh4 | |
| parent | 5a668651bf0da3891c46ea2cfcac227ded783a5a (diff) | |
| download | linux-8d5fb297cc8f9f7de2840864e497bc38330abba6.tar.xz | |
sh: Split out cache status bits per-CPU family.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/cpu-sh4')
| -rw-r--r-- | include/asm-sh/cpu-sh4/cache.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-sh4/cache.h b/include/asm-sh/cpu-sh4/cache.h index f92b20a..1c61ebf 100644 --- a/include/asm-sh/cpu-sh4/cache.h +++ b/include/asm-sh/cpu-sh4/cache.h @@ -12,6 +12,11 @@ #define L1_CACHE_SHIFT 5 +#define SH_CACHE_VALID 1 +#define SH_CACHE_UPDATED 2 +#define SH_CACHE_COMBINED 4 +#define SH_CACHE_ASSOC 8 + #define CCR 0xff00001c /* Address of Cache Control Register */ #define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */ #define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/ |