mmc: sdhci-of-esdhc: Workaround for reducing the maximum speed on ls1021atwr

In SDHC high speed AC timing, the tshivkh parameter
is defined as input setup times:SDHC_CMD, SDHC_DATx,
to SDHC_CLK. The value of the tshivkh should be 2.5 ns
considering the round trip delay, board/data skew.
However, because of this erratum, it needs
at least 4.1 ns.

eSDHC cannot run at the maximum clock speed for the
high speed mode, or there is a limit on the length
of the trace on the board for data, command, and
clock lines of the SDHC.

Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>

0 files changed, 0 insertions, 0 deletions