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| author | Jacob Shin <jacob.w.shin@gmail.com> | 2006-06-26 11:58:47 (GMT) |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-26 17:48:20 (GMT) |
| commit | 17fc14ff1bdbc393e1cf4f6fd1e1e53d72ab9fe5 (patch) | |
| tree | 9992a9079f4792f423f1e421d93814509b2c7d88 /include | |
| parent | c38bfdc85aae0c6d1458269c0e063c2f4a116711 (diff) | |
| download | linux-17fc14ff1bdbc393e1cf4f6fd1e1e53d72ab9fe5.tar.xz | |
[PATCH] x86_64: apic support for extended apic interrupt
Add support for extended APIC LVT found in future AMD processors.
Signed-off-by: Jacob Shin <jacob.shin@amd.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-x86_64/apic.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/include/asm-x86_64/apic.h b/include/asm-x86_64/apic.h index c9e6c25..9d43ac8 100644 --- a/include/asm-x86_64/apic.h +++ b/include/asm-x86_64/apic.h @@ -84,9 +84,18 @@ extern void disable_APIC_timer(void); extern void enable_APIC_timer(void); extern void clustered_apic_check(void); +extern void setup_APIC_extened_lvt(unsigned char lvt_off, unsigned char vector, + unsigned char msg_type, unsigned char mask); + +#define K8_APIC_EXT_LVT_BASE 0x500 +#define K8_APIC_EXT_INT_MSG_FIX 0x0 +#define K8_APIC_EXT_INT_MSG_SMI 0x2 +#define K8_APIC_EXT_INT_MSG_NMI 0x4 +#define K8_APIC_EXT_INT_MSG_EXT 0x7 +#define K8_APIC_EXT_LVT_ENTRY_THRESHOLD 0 + extern int disable_timer_pin_1; -extern void setup_threshold_lvt(unsigned long lvt_off); void smp_send_timer_broadcast_ipi(void); void switch_APIC_timer_to_ipi(void *cpumask); |