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| author | Felipe Balbi <balbi@ti.com> | 2011-10-14 10:00:30 (GMT) |
|---|---|---|
| committer | Felipe Balbi <balbi@ti.com> | 2011-12-12 09:48:34 (GMT) |
| commit | fae2b904aa85beecd0950026de28921ae65fb3da (patch) | |
| tree | b8f5a84150854fedb435b4c90948b2ae10ef1178 /include | |
| parent | d39ee7be2aaf0a53d7b5f43c13571bac95f7cc0c (diff) | |
| download | linux-fae2b904aa85beecd0950026de28921ae65fb3da.tar.xz | |
usb: dwc3: workaround: U1/U2 -> U0 transiton
RTL revisions <1.83a have an issue where, depending
on the link partner, the USB link might do multiple
entry/exit of low power states before a transfer
takes place causing degraded throughput.
The suggested workaround is to clear bits
12:9 of DCTL register if we see a transition
from U1|U2 to U0 and only re-enable that on
a transfer complete IRQ and we have no pending
transfers on any of the enabled endpoints.
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions