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| author | Kirill A. Shutemov <kirill.shutemov@linux.intel.com> | 2013-12-23 12:16:58 (GMT) |
|---|---|---|
| committer | H. Peter Anvin <hpa@linux.intel.com> | 2014-01-03 22:35:42 (GMT) |
| commit | dd360393f4d948eb518372316e52101cf3b44212 (patch) | |
| tree | 7b664120f6ea4de3adb75acc9d05fbf15356f1cc /kernel/locking/lockdep.c | |
| parent | 802eee95bde72fd0cd0f3a5b2098375a487d1eda (diff) | |
| download | linux-dd360393f4d948eb518372316e52101cf3b44212.tar.xz | |
x86, cpu: Detect more TLB configuration
The Intel Software Developer’s Manual covers few more TLB
configurations exposed as CPUID 2 descriptors:
61H Instruction TLB: 4 KByte pages, fully associative, 48 entries
63H Data TLB: 1 GByte pages, 4-way set associative, 4 entries
76H Instruction TLB: 2M/4M pages, fully associative, 8 entries
B5H Instruction TLB: 4KByte pages, 8-way set associative, 64 entries
B6H Instruction TLB: 4KByte pages, 8-way set associative, 128 entries
C1H Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries
C2H DTLB DTLB: 2 MByte/$MByte pages, 4-way associative, 16 entries
Let's detect them as well.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Link: http://lkml.kernel.org/r/1387801018-14499-1-git-send-email-kirill.shutemov@linux.intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'kernel/locking/lockdep.c')
0 files changed, 0 insertions, 0 deletions