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| author | Andre Przywara <andre.przywara@arm.com> | 2016-02-16 10:46:08 (GMT) |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2016-02-22 03:44:49 (GMT) |
| commit | d331328da6b719e4ffb3b43125bbe540755239ad (patch) | |
| tree | c2d7afe11f2676edb6f4e76eee6fa362fbe6ca08 /net/hsr/hsr_main.h | |
| parent | b26803ebfba8d81e2e8fb392c1248df2ebd1ba83 (diff) | |
| download | linux-d331328da6b719e4ffb3b43125bbe540755239ad.tar.xz | |
clk: sunxi: Improve divs_clk error handling and reporting
We catch errors in the base clock registration, failure to ioremap
and failures in the final of_clk_add_provider() call.
Also we unmap the registers when we need to rollback.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'net/hsr/hsr_main.h')
0 files changed, 0 insertions, 0 deletions