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authorSeungwon Jeon <tgih.jun@samsung.com>2012-05-22 04:01:21 (GMT)
committerChris Ball <cjb@laptop.org>2012-06-06 13:38:51 (GMT)
commite419990b5e811027b1552cbc5b76a6cc180f7f48 (patch)
tree12791ff201b9e56f74caaa86c22ce0964a8effcc /net/wimax
parentfda5f736864c46324dbc50246ef1ca0e84ebf4ae (diff)
downloadlinux-e419990b5e811027b1552cbc5b76a6cc180f7f48.tar.xz
mmc: dw_mmc: correct the calculation for CLKDIV
In case of "host->bus_hz < slot->clock", divider value is miscalculated. And clock divider register value is multiple of 2. If calculated divider value is odd number, result can be over-clocking. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Acked-by: Will Newton <will.newton@gmail.com> Signed-off-by: Chris Ball <cjb@laptop.org>
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