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authorBharat Bhushan <Bharat.Bhushan@freescale.com>2014-08-06 06:38:51 (GMT)
committerAlexander Graf <agraf@suse.de>2014-09-22 08:11:29 (GMT)
commit9fee7563cdb535596c48e7b05383d75590a64418 (patch)
treeee8aba839f173d156ec4e345ac1d4b4c3556c1ba /scripts/rt-tester
parentf51770ed465e6eb41da7fa16fd92eb67069600cf (diff)
downloadlinux-9fee7563cdb535596c48e7b05383d75590a64418.tar.xz
KVM: PPC: BOOKE: allow debug interrupt at "debug level"
Debug interrupt can be either "critical level" or "debug level". There are separate set of save/restore registers used for different level. Example: DSRR0/DSRR1 are used for "debug level" and CSRR0/CSRR1 are used for critical level debug interrupt. Using CPU_FTR_DEBUG_LVL_EXC to decide which interrupt level to be used. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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