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authorXiubo Li <Li.Xiubo@freescale.com>2014-02-11 07:42:49 (GMT)
committerMark Brown <broonie@linaro.org>2014-02-12 15:32:22 (GMT)
commiteaba603fc7c6281908c316d9e58de688943d58be (patch)
treeae110499c00a79e1ebd7a111687fe7072da0fc0a /sound/soc/fsl/fsl_esai.c
parent33529ec94f7cb25f6c98908eefde42a1e8d4e67a (diff)
downloadlinux-eaba603fc7c6281908c316d9e58de688943d58be.tar.xz
ASoC: fsl-esai: big-endian support
For most platforms, the CPU and ESAI device is in the same endianess mode. While for the LS1 platform, the CPU is in LE mode and the ESAI is in BE mode. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Acked-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'sound/soc/fsl/fsl_esai.c')
-rw-r--r--sound/soc/fsl/fsl_esai.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index f55341e..d8e13ab 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -678,7 +678,7 @@ static bool fsl_esai_writeable_reg(struct device *dev, unsigned int reg)
}
}
-static const struct regmap_config fsl_esai_regmap_config = {
+static struct regmap_config fsl_esai_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
@@ -704,6 +704,9 @@ static int fsl_esai_probe(struct platform_device *pdev)
esai_priv->pdev = pdev;
strcpy(esai_priv->name, np->name);
+ if (of_property_read_bool(np, "big-endian"))
+ fsl_esai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
+
/* Get the addresses and IRQ */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(&pdev->dev, res);