diff options
| author | Bard Liao <bardliao@realtek.com> | 2014-12-15 07:42:34 (GMT) |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2014-12-22 18:44:14 (GMT) |
| commit | 026e73683ad5665a45b01ca1a221fa87e0e8e6fb (patch) | |
| tree | 2ba7cb72330c6be77f901db510b27a7d393d7d01 /sound | |
| parent | f2ecf2ef59b57bd495c40d8a3e9d03e80f66afa4 (diff) | |
| download | linux-026e73683ad5665a45b01ca1a221fa87e0e8e6fb.tar.xz | |
ASoC: rt5670: Keep sysclk on if JD func is used
System clock is necessary for rt5670 JD function. We assume system
clock source will be set in machine driver. So there are two things
left we should do in codec driver.
1. Set sysclk to codec internal clock in probe since machine driver
may not do that before JD function is registered.
2. Power up PLL once sysclk source is switched to PLL.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/codecs/rt5670.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/sound/soc/codecs/rt5670.c b/sound/soc/codecs/rt5670.c index 78d85de..0a027bc 100644 --- a/sound/soc/codecs/rt5670.c +++ b/sound/soc/codecs/rt5670.c @@ -2190,6 +2190,13 @@ static int rt5670_set_dai_sysclk(struct snd_soc_dai *dai, if (freq == rt5670->sysclk && clk_id == rt5670->sysclk_src) return 0; + if (rt5670->pdata.jd_mode) { + if (clk_id == RT5670_SCLK_S_PLL1) + snd_soc_dapm_force_enable_pin(&codec->dapm, "PLL1"); + else + snd_soc_dapm_disable_pin(&codec->dapm, "PLL1"); + snd_soc_dapm_sync(&codec->dapm); + } switch (clk_id) { case RT5670_SCLK_S_MCLK: reg_val |= RT5670_SCLK_SRC_MCLK; @@ -2628,6 +2635,10 @@ static int rt5670_i2c_probe(struct i2c_client *i2c, } if (rt5670->pdata.jd_mode) { + regmap_update_bits(rt5670->regmap, RT5670_GLB_CLK, + RT5670_SCLK_SRC_MASK, RT5670_SCLK_SRC_RCCLK); + rt5670->sysclk = 0; + rt5670->sysclk_src = RT5670_SCLK_S_RCCLK; regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG1, RT5670_PWR_MB, RT5670_PWR_MB); regmap_update_bits(rt5670->regmap, RT5670_PWR_ANLG2, |