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| author | Minghuan Lian <Minghuan.Lian@nxp.com> | 2017-01-17 06:38:32 (GMT) |
|---|---|---|
| committer | Xie Xiaobo <xiaobo.xie@nxp.com> | 2017-09-25 07:25:29 (GMT) |
| commit | 78b747110fcd3cbb96f026f4c4af8d9d96ea5a31 (patch) | |
| tree | 1933bf30a858d5e62360f533db9fbc6eeacfe5dc /usr | |
| parent | 4026107b6dd6fcde49d0c958ac386383a3df60ee (diff) | |
| download | linux-78b747110fcd3cbb96f026f4c4af8d9d96ea5a31.tar.xz | |
irqchip/ls-scfg-msi: add LS1043a v1.1 MSI support
A MSI controller of LS1043a v1.0 only includes one MSIR and
is assigned one GIC interrupt. In order to support affinity,
LS1043a v1.1 MSI is assigned 4 MSIRs and 4 GIC interrupts.
But the MSIR has the different offset and only supports 8 MSIs.
The bits between variable bit_start and bit_end in structure
ls_scfg_msir are used to show 8 MSI interrupts. msir_irqs and
msir_base are added to describe the difference of MSI between
LS1043a v1.1 and other SoCs.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Diffstat (limited to 'usr')
0 files changed, 0 insertions, 0 deletions