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author | Marc Zyngier <marc.zyngier@arm.com> | 2016-05-25 14:26:35 (GMT) |
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committer | Christoffer Dall <christoffer.dall@linaro.org> | 2016-05-31 14:12:15 (GMT) |
commit | df7942d17e1623d7358fe895377293637de5521b (patch) | |
tree | 7fe65e36f85673413127aac9bcf24f1c98d73c88 /virt/kvm/arm/vgic/vgic-v3.c | |
parent | fa89c77e891917b5913f9be080f9131a9457bb3e (diff) | |
download | linux-df7942d17e1623d7358fe895377293637de5521b.tar.xz |
KVM: arm/arm64: vgic-v2: Always resample level interrupts
When reading back from the list registers, we need to perform
two actions for level interrupts:
1) clear the soft-pending bit if the interrupt is not pending
anymore *in the list register*
2) resample the line level and propagate it to the pending state
But these two actions shouldn't be linked, and we should *always*
resample the line level, no matter what state is in the list
register. Otherwise, we may end-up injecting spurious interrupts
that have been already retired.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Diffstat (limited to 'virt/kvm/arm/vgic/vgic-v3.c')
0 files changed, 0 insertions, 0 deletions