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| author | Nicolas Ferre <nicolas.ferre@atmel.com> | 2013-05-14 03:00:16 (GMT) |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2013-05-14 20:04:02 (GMT) |
| commit | 581df9e1944194bfcabc57e1efae79b0fe171d6f (patch) | |
| tree | c9965f5d51aaadee4bbaf3b1608876ac743015b3 /virt | |
| parent | faff57a92ba1d7247c5e86ecea2886d2c9d54507 (diff) | |
| download | linux-581df9e1944194bfcabc57e1efae79b0fe171d6f.tar.xz | |
net/macb: fix ISR clear-on-write behavior only for some SoC
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using the Design Configuration Register 1 information and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <hein_tibosch@yahoo.es>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: Hein Tibosch <hein_tibosch@yahoo.es>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'virt')
0 files changed, 0 insertions, 0 deletions