diff options
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 1 | ||||
| -rw-r--r-- | drivers/clk/tegra/clk-tegra114.c | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index bfef9ab..f9950dd 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -1223,6 +1223,7 @@ static long _pllre_calc_rate(struct tegra_clk_pll *pll, return output_rate; } + static int clk_pllre_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index d076642..75d8af6 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -1263,6 +1263,7 @@ static void tegra114_wait_cpu_in_reset(u32 cpu) cpu_relax(); } while (!(reg & (1 << cpu))); /* check CPU been reset or not */ } + static void tegra114_disable_cpu_clock(u32 cpu) { /* flow controller would take care in the power sequence. */ @@ -1351,7 +1352,6 @@ static void __init tegra114_clock_apply_init_table(void) tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX); } - /** * tegra114_car_barrier - wait for pending writes to the CAR to complete * |