diff options
-rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/stmmac.h | 13 | ||||
-rw-r--r-- | drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 5 |
2 files changed, 11 insertions, 7 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h index 9f2435c..db2de9a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h @@ -107,7 +107,7 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device, #ifdef CONFIG_HAVE_CLK static inline int stmmac_clk_enable(struct stmmac_priv *priv) { - if (priv->stmmac_clk) + if (!IS_ERR(priv->stmmac_clk)) return clk_enable(priv->stmmac_clk); return 0; @@ -115,17 +115,18 @@ static inline int stmmac_clk_enable(struct stmmac_priv *priv) static inline void stmmac_clk_disable(struct stmmac_priv *priv) { - if (priv->stmmac_clk) - clk_disable(priv->stmmac_clk); + if (IS_ERR(priv->stmmac_clk)) + return; + + clk_disable(priv->stmmac_clk); } static inline int stmmac_clk_get(struct stmmac_priv *priv) { priv->stmmac_clk = clk_get(priv->device, NULL); - if (IS_ERR(priv->stmmac_clk)) { - pr_err("%s: ERROR clk_get failed\n", __func__); + if (IS_ERR(priv->stmmac_clk)) return PTR_ERR(priv->stmmac_clk); - } + return 0; } #else diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index efc42e1..1a4cf81 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -168,6 +168,9 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv) #ifdef CONFIG_HAVE_CLK u32 clk_rate; + if (IS_ERR(priv->stmmac_clk)) + return; + clk_rate = clk_get_rate(priv->stmmac_clk); /* Platform provided default clk_csr would be assumed valid @@ -1923,7 +1926,7 @@ struct stmmac_priv *stmmac_dvr_probe(struct device *device, } if (stmmac_clk_get(priv)) - goto error; + pr_warning("%s: warning: cannot get CSR clock\n", __func__); /* If a specific clk_csr value is passed from the platform * this means that the CSR Clock Range selection cannot be |