diff options
Diffstat (limited to 'arch/arm/mach-omap2')
| -rw-r--r-- | arch/arm/mach-omap2/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap-wakeupgen.c | 5 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod.h | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 364 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_reset.c | 65 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/powerdomains7xx_data.c | 82 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/soc.h | 140 |
9 files changed, 505 insertions, 169 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 0ba6a0e..04e276c 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ +ccflags-y := -I$(srctree)/$(src)/include \ -I$(srctree)/arch/arm/plat-omap/include # Common support diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c index 2c04f27..0c47543 100644 --- a/arch/arm/mach-omap2/omap-wakeupgen.c +++ b/arch/arm/mach-omap2/omap-wakeupgen.c @@ -327,6 +327,11 @@ static int irq_cpu_hotplug_notify(struct notifier_block *self, { unsigned int cpu = (unsigned int)hcpu; + /* + * Corresponding FROZEN transitions do not have to be handled, + * they are handled by at a higher level + * (drivers/cpuidle/coupled.c). + */ switch (action) { case CPU_ONLINE: wakeupgen_irqmask_all(cpu, 0); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2af6ff6..83cb527 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -2207,15 +2207,15 @@ static int _idle(struct omap_hwmod *oh) pr_debug("omap_hwmod: %s: idling\n", oh->name); + if (_are_all_hardreset_lines_asserted(oh)) + return 0; + if (oh->_state != _HWMOD_STATE_ENABLED) { WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", oh->name); return -EINVAL; } - if (_are_all_hardreset_lines_asserted(oh)) - return 0; - if (oh->class->sysc) _idle_sysc(oh); _del_initiator_dep(oh, mpu_oh); @@ -2262,6 +2262,9 @@ static int _shutdown(struct omap_hwmod *oh) int ret, i; u8 prev_state; + if (_are_all_hardreset_lines_asserted(oh)) + return 0; + if (oh->_state != _HWMOD_STATE_IDLE && oh->_state != _HWMOD_STATE_ENABLED) { WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", @@ -2269,9 +2272,6 @@ static int _shutdown(struct omap_hwmod *oh) return -EINVAL; } - if (_are_all_hardreset_lines_asserted(oh)) - return 0; - pr_debug("omap_hwmod: %s: disabling\n", oh->name); if (oh->class->pre_shutdown) { diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index 7c7a311..4041bad 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -754,6 +754,8 @@ const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); */ extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh); +void omap_hwmod_rtc_unlock(struct omap_hwmod *oh); +void omap_hwmod_rtc_lock(struct omap_hwmod *oh); /* * Chip variant-specific hwmod init routines - XXX should be converted diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c index 907a452b..aed3362 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c @@ -918,6 +918,8 @@ static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = { static struct omap_hwmod_class am33xx_rtc_hwmod_class = { .name = "rtc", .sysc = &am33xx_rtc_sysc, + .unlock = &omap_hwmod_rtc_unlock, + .lock = &omap_hwmod_rtc_lock, }; struct omap_hwmod am33xx_rtc_hwmod = { diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 9442d89..d0e7e525 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -383,6 +383,68 @@ static struct omap_hwmod dra7xx_dcan2_hwmod = { }, }; +/* pwmss */ +static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = { + .rev_offs = 0x0, + .sysc_offs = 0x4, + .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +/* + * epwmss class + */ +static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = { + .name = "epwmss", + .sysc = &dra7xx_epwmss_sysc, +}; + +/* epwmss0 */ +static struct omap_hwmod dra7xx_epwmss0_hwmod = { + .name = "epwmss0", + .class = &dra7xx_epwmss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET, + }, + }, +}; + +/* epwmss1 */ +static struct omap_hwmod dra7xx_epwmss1_hwmod = { + .name = "epwmss1", + .class = &dra7xx_epwmss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET, + }, + }, +}; + +/* epwmss2 */ +static struct omap_hwmod dra7xx_epwmss2_hwmod = { + .name = "epwmss2", + .class = &dra7xx_epwmss_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .modulemode = MODULEMODE_SWCTRL, + .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET, + }, + }, +}; + /* * 'dma' class * @@ -1374,6 +1436,52 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = { .sysc = &dra7xx_mcasp_sysc, }; +/* mcasp1 */ +static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" }, + { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp1_hwmod = { + .name = "mcasp1", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "ipu_clkdm", + .main_clk = "mcasp1_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks), +}; + +/* mcasp2 */ +static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" }, + { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp2_hwmod = { + .name = "mcasp2", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp2_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks), +}; + /* mcasp3 */ static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = { { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" }, @@ -1396,6 +1504,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = { .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks), }; +/* mcasp4 */ +static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp4_hwmod = { + .name = "mcasp4", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp4_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks), +}; + +/* mcasp5 */ +static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp5_hwmod = { + .name = "mcasp5", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp5_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks), +}; + +/* mcasp6 */ +static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp6_hwmod = { + .name = "mcasp6", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp6_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks), +}; + +/* mcasp7 */ +static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp7_hwmod = { + .name = "mcasp7", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp7_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp7_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks), +}; + +/* mcasp8 */ +static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = { + { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" }, +}; + +static struct omap_hwmod dra7xx_mcasp8_hwmod = { + .name = "mcasp8", + .class = &dra7xx_mcasp_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "mcasp8_aux_gfclk_mux", + .flags = HWMOD_OPT_CLKS_NEEDED, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mcasp8_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks), +}; + /* * 'mmc' class * @@ -1707,6 +1925,8 @@ static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = { static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = { .name = "rtcss", .sysc = &dra7xx_rtcss_sysc, + .unlock = &omap_hwmod_rtc_unlock, + .lock = &omap_hwmod_rtc_lock, }; /* rtcss */ @@ -2065,6 +2285,20 @@ static struct omap_hwmod dra7xx_timer11_hwmod = { }, }; +/* timer12 */ +static struct omap_hwmod dra7xx_timer12_hwmod = { + .name = "timer12", + .class = &dra7xx_timer_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "secure_32k_clk_src_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET, + }, + }, +}; + /* timer13 */ static struct omap_hwmod dra7xx_timer13_hwmod = { .name = "timer13", @@ -2726,6 +2960,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> mcasp1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mcasp1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mcasp1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> mcasp2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_mcasp2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per2 -> mcasp3 */ static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = { .master = &dra7xx_l4_per2_hwmod, @@ -2742,6 +3008,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> mcasp4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp4_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp5 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp5_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp6 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp6_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp7 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp7_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> mcasp8 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_mcasp8_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per1 -> elm */ static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = { .master = &dra7xx_l4_per1_hwmod, @@ -3281,6 +3587,14 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_wkup -> timer12 */ +static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = { + .master = &dra7xx_l4_wkup_hwmod, + .slave = &dra7xx_timer12_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_per3 -> timer13 */ static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = { .master = &dra7xx_l4_per3_hwmod, @@ -3465,6 +3779,30 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_per2 -> epwmss0 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_epwmss0_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU, +}; + +/* l4_per2 -> epwmss1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_epwmss1_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU, +}; + +/* l4_per2 -> epwmss2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_epwmss2_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU, +}; + static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__dmm, &dra7xx_l3_main_2__l3_instr, @@ -3484,8 +3822,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_wkup__dcan1, &dra7xx_l4_per2__dcan2, &dra7xx_l4_per2__cpgmac0, + &dra7xx_l4_per2__mcasp1, + &dra7xx_l3_main_1__mcasp1, + &dra7xx_l4_per2__mcasp2, + &dra7xx_l3_main_1__mcasp2, &dra7xx_l4_per2__mcasp3, &dra7xx_l3_main_1__mcasp3, + &dra7xx_l4_per2__mcasp4, + &dra7xx_l4_per2__mcasp5, + &dra7xx_l4_per2__mcasp6, + &dra7xx_l4_per2__mcasp7, + &dra7xx_l4_per2__mcasp8, &dra7xx_gmac__mdio, &dra7xx_l4_cfg__dma_system, &dra7xx_l3_main_1__tpcc, @@ -3577,9 +3924,19 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { &dra7xx_l3_main_1__vcp2, &dra7xx_l4_per2__vcp2, &dra7xx_l4_wkup__wd_timer2, + &dra7xx_l4_per2__epwmss0, + &dra7xx_l4_per2__epwmss1, + &dra7xx_l4_per2__epwmss2, + NULL, +}; + +/* GP-only hwmod links */ +static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = { + &dra7xx_l4_wkup__timer12, NULL, }; +/* SoC variant specific hwmod links */ static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = { &dra7xx_l4_per3__usb_otg_ss4, NULL, @@ -3597,9 +3954,12 @@ int __init dra7xx_hwmod_init(void) ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); if (!ret && soc_is_dra74x()) - return omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); + ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs); else if (!ret && soc_is_dra72x()) - return omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); + ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs); + + if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP) + ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs); return ret; } diff --git a/arch/arm/mach-omap2/omap_hwmod_reset.c b/arch/arm/mach-omap2/omap_hwmod_reset.c index 65e186c..b68f9c0 100644 --- a/arch/arm/mach-omap2/omap_hwmod_reset.c +++ b/arch/arm/mach-omap2/omap_hwmod_reset.c @@ -29,6 +29,16 @@ #include <sound/aess.h> #include "omap_hwmod.h" +#include "common.h" + +#define OMAP_RTC_STATUS_REG 0x44 +#define OMAP_RTC_KICK0_REG 0x6c +#define OMAP_RTC_KICK1_REG 0x70 + +#define OMAP_RTC_KICK0_VALUE 0x83E70B13 +#define OMAP_RTC_KICK1_VALUE 0x95A4F1E0 +#define OMAP_RTC_STATUS_BUSY BIT(0) +#define OMAP_RTC_MAX_READY_TIME 50 /** * omap_hwmod_aess_preprogram - enable AESS internal autogating @@ -51,3 +61,58 @@ int omap_hwmod_aess_preprogram(struct omap_hwmod *oh) return 0; } + +/** + * omap_rtc_wait_not_busy - Wait for the RTC BUSY flag + * @oh: struct omap_hwmod * + * + * For updating certain RTC registers, the MPU must wait + * for the BUSY status in OMAP_RTC_STATUS_REG to become zero. + * Once the BUSY status is zero, there is a 15 microseconds access + * period in which the MPU can program. + */ +static void omap_rtc_wait_not_busy(struct omap_hwmod *oh) +{ + int i; + + /* BUSY may stay active for 1/32768 second (~30 usec) */ + omap_test_timeout(omap_hwmod_read(oh, OMAP_RTC_STATUS_REG) + & OMAP_RTC_STATUS_BUSY, OMAP_RTC_MAX_READY_TIME, i); + /* now we have ~15 microseconds to read/write various registers */ +} + +/** + * omap_hwmod_rtc_unlock - Unlock the Kicker mechanism. + * @oh: struct omap_hwmod * + * + * RTC IP have kicker feature. This prevents spurious writes to its registers. + * In order to write into any of the RTC registers, KICK values has te be + * written in respective KICK registers. This is needed for hwmod to write into + * sysconfig register. + */ +void omap_hwmod_rtc_unlock(struct omap_hwmod *oh) +{ + local_irq_disable(); + omap_rtc_wait_not_busy(oh); + omap_hwmod_write(OMAP_RTC_KICK0_VALUE, oh, OMAP_RTC_KICK0_REG); + omap_hwmod_write(OMAP_RTC_KICK1_VALUE, oh, OMAP_RTC_KICK1_REG); + local_irq_enable(); +} + +/** + * omap_hwmod_rtc_lock - Lock the Kicker mechanism. + * @oh: struct omap_hwmod * + * + * RTC IP have kicker feature. This prevents spurious writes to its registers. + * Once the RTC registers are written, KICK mechanism needs to be locked, + * in order to prevent any spurious writes. This function locks back the RTC + * registers once hwmod completes its write into sysconfig register. + */ +void omap_hwmod_rtc_lock(struct omap_hwmod *oh) +{ + local_irq_disable(); + omap_rtc_wait_not_busy(oh); + omap_hwmod_write(0x0, oh, OMAP_RTC_KICK0_REG); + omap_hwmod_write(0x0, oh, OMAP_RTC_KICK1_REG); + local_irq_enable(); +} diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c index 287a203..0ec2d00 100644 --- a/arch/arm/mach-omap2/powerdomains7xx_data.c +++ b/arch/arm/mach-omap2/powerdomains7xx_data.c @@ -35,7 +35,7 @@ static struct powerdomain iva_7xx_pwrdm = { .name = "iva_pwrdm", .prcm_offs = DRA7XX_PRM_IVA_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 4, .pwrsts_mem_ret = { @@ -45,10 +45,10 @@ static struct powerdomain iva_7xx_pwrdm = { [3] = PWRSTS_OFF_RET, /* tcm2_mem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* hwa_mem */ - [1] = PWRSTS_OFF_RET, /* sl2_mem */ - [2] = PWRSTS_OFF_RET, /* tcm1_mem */ - [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + [0] = PWRSTS_ON, /* hwa_mem */ + [1] = PWRSTS_ON, /* sl2_mem */ + [2] = PWRSTS_ON, /* tcm1_mem */ + [3] = PWRSTS_ON, /* tcm2_mem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -75,7 +75,7 @@ static struct powerdomain ipu_7xx_pwrdm = { .name = "ipu_pwrdm", .prcm_offs = DRA7XX_PRM_IPU_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 2, .pwrsts_mem_ret = { @@ -83,8 +83,8 @@ static struct powerdomain ipu_7xx_pwrdm = { [1] = PWRSTS_OFF_RET, /* periphmem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* aessmem */ - [1] = PWRSTS_OFF_RET, /* periphmem */ + [0] = PWRSTS_ON, /* aessmem */ + [1] = PWRSTS_ON, /* periphmem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -94,14 +94,14 @@ static struct powerdomain dss_7xx_pwrdm = { .name = "dss_pwrdm", .prcm_offs = DRA7XX_PRM_DSS_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts = PWRSTS_OFF_ON, .pwrsts_logic_ret = PWRSTS_OFF, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* dss_mem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* dss_mem */ + [0] = PWRSTS_ON, /* dss_mem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -112,15 +112,15 @@ static struct powerdomain l4per_7xx_pwrdm = { .prcm_offs = DRA7XX_PRM_L4PER_INST, .prcm_partition = DRA7XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 2, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* nonretained_bank */ [1] = PWRSTS_OFF_RET, /* retained_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* nonretained_bank */ - [1] = PWRSTS_OFF_RET, /* retained_bank */ + [0] = PWRSTS_ON, /* nonretained_bank */ + [1] = PWRSTS_ON, /* retained_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -136,7 +136,7 @@ static struct powerdomain gpu_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* gpu_mem */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* gpu_mem */ + [0] = PWRSTS_ON, /* gpu_mem */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -160,7 +160,7 @@ static struct powerdomain core_7xx_pwrdm = { .name = "core_pwrdm", .prcm_offs = DRA7XX_PRM_CORE_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_INA_ON, + .pwrsts = PWRSTS_ON, .pwrsts_logic_ret = PWRSTS_RET, .banks = 5, .pwrsts_mem_ret = { @@ -171,11 +171,11 @@ static struct powerdomain core_7xx_pwrdm = { [4] = PWRSTS_OFF_RET, /* ipu_unicache */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* core_nret_bank */ - [1] = PWRSTS_OFF_RET, /* core_ocmram */ - [2] = PWRSTS_OFF_RET, /* core_other_bank */ - [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ - [4] = PWRSTS_OFF_RET, /* ipu_unicache */ + [0] = PWRSTS_ON, /* core_nret_bank */ + [1] = PWRSTS_ON, /* core_ocmram */ + [2] = PWRSTS_ON, /* core_other_bank */ + [3] = PWRSTS_ON, /* ipu_l2ram */ + [4] = PWRSTS_ON, /* ipu_unicache */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -225,14 +225,14 @@ static struct powerdomain vpe_7xx_pwrdm = { .name = "vpe_pwrdm", .prcm_offs = DRA7XX_PRM_VPE_INST, .prcm_partition = DRA7XX_PRM_PARTITION, - .pwrsts = PWRSTS_OFF_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts = PWRSTS_OFF_ON, + .pwrsts_logic_ret = PWRSTS_OFF, .banks = 1, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* vpe_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* vpe_bank */ + [0] = PWRSTS_ON, /* vpe_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -250,8 +250,8 @@ static struct powerdomain mpu_7xx_pwrdm = { [1] = PWRSTS_RET, /* mpu_ram */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* mpu_l2 */ - [1] = PWRSTS_OFF_RET, /* mpu_ram */ + [0] = PWRSTS_ON, /* mpu_l2 */ + [1] = PWRSTS_ON, /* mpu_ram */ }, }; @@ -261,7 +261,7 @@ static struct powerdomain l3init_7xx_pwrdm = { .prcm_offs = DRA7XX_PRM_L3INIT_INST, .prcm_partition = DRA7XX_PRM_PARTITION, .pwrsts = PWRSTS_RET_ON, - .pwrsts_logic_ret = PWRSTS_OFF_RET, + .pwrsts_logic_ret = PWRSTS_RET, .banks = 3, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* gmac_bank */ @@ -269,9 +269,9 @@ static struct powerdomain l3init_7xx_pwrdm = { [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* gmac_bank */ - [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ - [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ + [0] = PWRSTS_ON, /* gmac_bank */ + [1] = PWRSTS_ON, /* l3init_bank1 */ + [2] = PWRSTS_ON, /* l3init_bank2 */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -287,7 +287,7 @@ static struct powerdomain eve3_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* eve3_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve3_bank */ + [0] = PWRSTS_ON, /* eve3_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -303,7 +303,7 @@ static struct powerdomain emu_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* emu_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* emu_bank */ + [0] = PWRSTS_ON, /* emu_bank */ }, }; @@ -320,9 +320,9 @@ static struct powerdomain dsp2_7xx_pwrdm = { [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* dsp2_edma */ - [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ - [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ + [0] = PWRSTS_ON, /* dsp2_edma */ + [1] = PWRSTS_ON, /* dsp2_l1 */ + [2] = PWRSTS_ON, /* dsp2_l2 */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -340,9 +340,9 @@ static struct powerdomain dsp1_7xx_pwrdm = { [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* dsp1_edma */ - [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ - [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ + [0] = PWRSTS_ON, /* dsp1_edma */ + [1] = PWRSTS_ON, /* dsp1_l1 */ + [2] = PWRSTS_ON, /* dsp1_l2 */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -358,7 +358,7 @@ static struct powerdomain cam_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* vip_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* vip_bank */ + [0] = PWRSTS_ON, /* vip_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -374,7 +374,7 @@ static struct powerdomain eve4_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* eve4_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve4_bank */ + [0] = PWRSTS_ON, /* eve4_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -390,7 +390,7 @@ static struct powerdomain eve2_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* eve2_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve2_bank */ + [0] = PWRSTS_ON, /* eve2_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; @@ -406,7 +406,7 @@ static struct powerdomain eve1_7xx_pwrdm = { [0] = PWRSTS_OFF_RET, /* eve1_bank */ }, .pwrsts_mem_on = { - [0] = PWRSTS_OFF_RET, /* eve1_bank */ + [0] = PWRSTS_ON, /* eve1_bank */ }, .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, }; diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 364418c..2aa01c2 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -39,82 +39,10 @@ #include <linux/of.h> /* - * Test if multicore OMAP support is needed + * OMAP2+ is always defined as ARCH_MULTIPLATFORM in Kconfig */ #undef MULTI_OMAP2 -#undef OMAP_NAME - -#ifdef CONFIG_ARCH_MULTIPLATFORM #define MULTI_OMAP2 -#endif -#ifdef CONFIG_SOC_OMAP2420 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2420 -# endif -#endif -#ifdef CONFIG_SOC_OMAP2430 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap2430 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP3 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap3 -# endif -#endif -#ifdef CONFIG_ARCH_OMAP4 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap4 -# endif -#endif - -#ifdef CONFIG_SOC_OMAP5 -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME omap5 -# endif -#endif - -#ifdef CONFIG_SOC_AM33XX -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME am33xx -# endif -#endif - -#ifdef CONFIG_SOC_AM43XX -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME am43xx -# endif -#endif - -#ifdef CONFIG_SOC_DRA7XX -# ifdef OMAP_NAME -# undef MULTI_OMAP2 -# define MULTI_OMAP2 -# else -# define OMAP_NAME DRA7XX -# endif -#endif /* * Omap device type i.e. EMU/HS/TST/GP/BAD @@ -242,11 +170,6 @@ IS_AM_SUBCLASS(437x, 0x437) IS_DRA_SUBCLASS(75x, 0x75) IS_DRA_SUBCLASS(72x, 0x72) -#define soc_is_omap24xx() 0 -#define soc_is_omap242x() 0 -#define soc_is_omap243x() 0 -#define soc_is_omap34xx() 0 -#define soc_is_omap343x() 0 #define soc_is_ti81xx() 0 #define soc_is_ti816x() 0 #define soc_is_ti814x() 0 @@ -265,46 +188,27 @@ IS_DRA_SUBCLASS(72x, 0x72) #define soc_is_dra74x() 0 #define soc_is_dra72x() 0 -#if defined(MULTI_OMAP2) -# if defined(CONFIG_ARCH_OMAP2) -# undef soc_is_omap24xx -# define soc_is_omap24xx() is_omap24xx() -# endif -# if defined (CONFIG_SOC_OMAP2420) -# undef soc_is_omap242x -# define soc_is_omap242x() is_omap242x() -# endif -# if defined (CONFIG_SOC_OMAP2430) -# undef soc_is_omap243x -# define soc_is_omap243x() is_omap243x() -# endif -# if defined(CONFIG_ARCH_OMAP3) -# undef soc_is_omap34xx -# undef soc_is_omap343x -# define soc_is_omap34xx() is_omap34xx() -# define soc_is_omap343x() is_omap343x() -# endif +#if defined(CONFIG_ARCH_OMAP2) +# define soc_is_omap24xx() is_omap24xx() #else -# if defined(CONFIG_ARCH_OMAP2) -# undef soc_is_omap24xx -# define soc_is_omap24xx() 1 -# endif -# if defined(CONFIG_SOC_OMAP2420) -# undef soc_is_omap242x -# define soc_is_omap242x() 1 -# endif -# if defined(CONFIG_SOC_OMAP2430) -# undef soc_is_omap243x -# define soc_is_omap243x() 1 -# endif -# if defined(CONFIG_ARCH_OMAP3) -# undef soc_is_omap34xx -# define soc_is_omap34xx() 1 -# endif -# if defined(CONFIG_SOC_OMAP3430) -# undef soc_is_omap343x -# define soc_is_omap343x() 1 -# endif +# define soc_is_omap24xx() 0 +#endif +#if defined(CONFIG_SOC_OMAP2420) +# define soc_is_omap242x() is_omap242x() +#else +# define soc_is_omap242x() 0 +#endif +#if defined(CONFIG_SOC_OMAP2430) +# define soc_is_omap243x() is_omap243x() +#else +# define soc_is_omap243x() 0 +#endif +#if defined(CONFIG_ARCH_OMAP3) +# define soc_is_omap34xx() is_omap34xx() +# define soc_is_omap343x() is_omap343x() +#else +# define soc_is_omap34xx() 0 +# define soc_is_omap343x() 0 #endif /* @@ -339,7 +243,6 @@ IS_OMAP_TYPE(3430, 0x3430) #define soc_is_omap5430() 0 /* These are needed for the common code */ -#ifdef CONFIG_ARCH_OMAP2PLUS #define soc_is_omap7xx() 0 #define soc_is_omap15xx() 0 #define soc_is_omap16xx() 0 @@ -350,7 +253,6 @@ IS_OMAP_TYPE(3430, 0x3430) #define soc_is_omap1710() 0 #define cpu_class_is_omap1() 0 #define cpu_class_is_omap2() 1 -#endif #if defined(CONFIG_ARCH_OMAP2) # undef soc_is_omap2420 |