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Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts169
1 files changed, 70 insertions, 99 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
index ad0ebb8..025f0f5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
@@ -1,8 +1,10 @@
/*
* Device Tree file for Freescale LS2080a RDB Board.
*
- * Copyright (C) 2015, Freescale Semiconductor
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
* Bhupesh Sharma <bhupesh.sharma@freescale.com>
*
* This file is dual-licensed: you can use it either under the terms
@@ -46,125 +48,94 @@
/dts-v1/;
-/include/ "fsl-ls2080a.dtsi"
+#include "fsl-ls2080a.dtsi"
+#include "fsl-ls208xa-rdb.dtsi"
/ {
model = "Freescale Layerscape 2080a RDB Board";
compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
- aliases {
- serial0 = &serial0;
- serial1 = &serial1;
- };
-
chosen {
stdout-path = "serial1:115200n8";
};
};
-&esdhc {
- status = "okay";
-};
-
-&ifc {
- status = "okay";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x5 0x80000000 0x08000000
- 0x2 0x0 0x5 0x30000000 0x00010000
- 0x3 0x0 0x5 0x20000000 0x00010000>;
-
- nor@0,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "cfi-flash";
- reg = <0x0 0x0 0x8000000>;
- bank-width = <2>;
- device-width = <1>;
+&emdio1 {
+ status = "disabled";
+ /* CS4340 PHYs */
+ mdio1_phy1: emdio1_phy@1 {
+ reg = <0x10>;
+ phy-connection-type = "xfi";
};
-
- nand@2,0 {
- compatible = "fsl,ifc-nand";
- reg = <0x2 0x0 0x10000>;
+ mdio1_phy2: emdio1_phy@2 {
+ reg = <0x11>;
+ phy-connection-type = "xfi";
};
-
- cpld@3,0 {
- reg = <0x3 0x0 0x10000>;
- compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
+ mdio1_phy3: emdio1_phy@3 {
+ reg = <0x12>;
+ phy-connection-type = "xfi";
};
-
-};
-
-&i2c0 {
- status = "okay";
- pca9547@75 {
- compatible = "nxp,pca9547";
- reg = <0x75>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x01>;
- rtc@68 {
- compatible = "dallas,ds3232";
- reg = <0x68>;
- };
- };
-
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x3>;
-
- adt7481@4c {
- compatible = "adi,adt7461";
- reg = <0x4c>;
- };
- };
+ mdio1_phy4: emdio1_phy@4 {
+ reg = <0x13>;
+ phy-connection-type = "xfi";
};
};
-&i2c1 {
- status = "disabled";
-};
-
-&i2c2 {
- status = "disabled";
-};
-
-&i2c3 {
- status = "disabled";
-};
-
-&dspi {
- status = "okay";
- dflash0: n25q512a {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "st,m25p80";
- spi-max-frequency = <3000000>;
- reg = <0>;
+&emdio2 {
+ /* AQR405 PHYs */
+ mdio2_phy1: emdio2_phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 1 0x4>; /* Level high type */
+ reg = <0x0>;
+ phy-connection-type = "xfi";
+ };
+ mdio2_phy2: emdio2_phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 2 0x4>; /* Level high type */
+ reg = <0x1>;
+ phy-connection-type = "xfi";
+ };
+ mdio2_phy3: emdio2_phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 4 0x4>; /* Level high type */
+ reg = <0x2>;
+ phy-connection-type = "xfi";
+ };
+ mdio2_phy4: emdio2_phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ interrupts = <0 5 0x4>; /* Level high type */
+ reg = <0x3>;
+ phy-connection-type = "xfi";
};
};
-&qspi {
- status = "disabled";
-};
+/* Update DPMAC connections to external PHYs, under the assumption of
+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
+ */
+/* Leave Cortina nodes commented out until driver is integrated
+ *&dpmac1 {
+ * phy-handle = <&mdio1_phy1>;
+ *};
+ *&dpmac2 {
+ * phy-handle = <&mdio1_phy2>;
+ *};
+ *&dpmac3 {
+ * phy-handle = <&mdio1_phy3>;
+ *};
+ *&dpmac4 {
+ * phy-handle = <&mdio1_phy4>;
+ *};
+ */
-&sata0 {
- status = "okay";
+&dpmac5 {
+ phy-handle = <&mdio2_phy1>;
};
-
-&sata1 {
- status = "okay";
+&dpmac6 {
+ phy-handle = <&mdio2_phy2>;
};
-
-&usb0 {
- status = "okay";
+&dpmac7 {
+ phy-handle = <&mdio2_phy3>;
};
-
-&usb1 {
- status = "okay";
+&dpmac8 {
+ phy-handle = <&mdio2_phy4>;
};