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Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 162 |
1 files changed, 162 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts new file mode 100644 index 0000000..1dbc7aa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts @@ -0,0 +1,162 @@ +/* + * Device Tree file for Freescale LS2088A QDS Board. + * + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * Abhimanyu Saini <abhimanyu.saini@nxp.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPLv2 or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "fsl-ls2088a.dtsi" +#include "fsl-ls208xa-qds.dtsi" + +/ { + model = "Freescale Layerscape 2088A QDS Board"; + compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ifc { + boardctrl: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; + reg = <3 0 0x300>; /* TODO check address */ + ranges = <0 3 0 0x300>; + + mdio_mux_emi1 { + compatible = "mdio-mux-mmioreg", "mdio-mux"; + mdio-parent-bus = <&emdio1>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1_MDIO */ + + #address-cells=<1>; + #size-cells = <0>; + + /* Child MDIO buses, one for each riser card: + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. + * VSC8234 PHYs on the riser cards. + */ + + mdio_mux3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + mdio0_phy12: mdio_phy0@1c { + reg = <0x1c>; + phy-connection-type = "sgmii"; + }; + mdio0_phy13: mdio_phy1@1d { + reg = <0x1d>; + phy-connection-type = "sgmii"; + }; + mdio0_phy14: mdio_phy2@1e { + reg = <0x1e>; + phy-connection-type = "sgmii"; + }; + mdio0_phy15: mdio_phy3@1f { + reg = <0x1f>; + phy-connection-type = "sgmii"; + }; + }; + }; + }; +}; + +&pcs_mdio1 { + pcs_phy1: ethernet-phy@0 { + backplane-mode = "10gbase-kr"; + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + fsl,lane-handle = <&serdes1>; + fsl,lane-reg = <0x9C0 0x40>;/* lane H */ + }; +}; + +&pcs_mdio2 { + pcs_phy2: ethernet-phy@0 { + backplane-mode = "10gbase-kr"; + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + fsl,lane-handle = <&serdes1>; + fsl,lane-reg = <0x980 0x40>;/* lane G */ + }; +}; + +&pcs_mdio3 { + pcs_phy3: ethernet-phy@0 { + backplane-mode = "10gbase-kr"; + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + fsl,lane-handle = <&serdes1>; + fsl,lane-reg = <0x940 0x40>;/* lane F */ + }; +}; + +&pcs_mdio4 { + pcs_phy4: ethernet-phy@0 { + backplane-mode = "10gbase-kr"; + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + fsl,lane-handle = <&serdes1>; + fsl,lane-reg = <0x900 0x40>;/* lane E */ + }; +}; + +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ +&dpmac9 { + phy-handle = <&mdio0_phy12>; +}; +&dpmac10 { + phy-handle = <&mdio0_phy13>; +}; +&dpmac11 { + phy-handle = <&mdio0_phy14>; +}; +&dpmac12 { + phy-handle = <&mdio0_phy15>; +}; |