diff options
Diffstat (limited to 'arch/arm64/boot/dts/mediatek')
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 3 | ||||
-rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8173.dtsi | 41 |
2 files changed, 24 insertions, 20 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 43d5401..d0ab012 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -16,7 +16,8 @@ #include "mt8173.dtsi" / { - model = "mediatek,mt8173-evb"; + model = "MediaTek MT8173 evaluation board"; + compatible = "mediatek,mt8173-evb", "mediatek,mt8173"; aliases { serial0 = &uart0; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 924fdb6..27237a1 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -91,13 +91,13 @@ compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 14 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; soc { @@ -106,14 +106,13 @@ compatible = "simple-bus"; ranges; - syscfg_pctl_a: syscfg_pctl_a@10005000 { - compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; - reg = <0 0x10005000 0 0x1000>; - }; - - pio: pinctrl@0x10005000 { + /* + * Pinctrl access register at 0x10005000 through regmap. + * Register 0x1000b000 is used by EINT. + */ + pio: pinctrl@10005000 { compatible = "mediatek,mt8173-pinctrl"; - reg = <0 0x1000B000 0 0x1000>; + reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; pins-are-numbered; gpio-controller; @@ -121,13 +120,18 @@ interrupt-controller; #interrupt-cells = <2>; interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + }; + + syscfg_pctl_a: syscfg_pctl_a@10005000 { + compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; }; sysirq: intpol-controller@10200620 { compatible = "mediatek,mt8173-sysirq", - "mediatek,mt6577-sysirq"; + "mediatek,mt6577-sysirq"; interrupt-controller; #interrupt-cells = <3>; interrupt-parent = <&gic>; @@ -149,7 +153,7 @@ uart0: serial@11002000 { compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; + "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x400>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; clocks = <&uart_clk>; @@ -158,7 +162,7 @@ uart1: serial@11003000 { compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; + "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x400>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; clocks = <&uart_clk>; @@ -167,7 +171,7 @@ uart2: serial@11004000 { compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; + "mediatek,mt6577-uart"; reg = <0 0x11004000 0 0x400>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; clocks = <&uart_clk>; @@ -176,13 +180,12 @@ uart3: serial@11005000 { compatible = "mediatek,mt8173-uart", - "mediatek,mt6577-uart"; + "mediatek,mt6577-uart"; reg = <0 0x11005000 0 0x400>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; clocks = <&uart_clk>; status = "disabled"; }; }; - }; |