diff options
Diffstat (limited to 'arch/arm')
30 files changed, 460 insertions, 105 deletions
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi index db8752f..d0eefc3 100644 --- a/arch/arm/boot/dts/alpine.dtsi +++ b/arch/arm/boot/dts/alpine.dtsi @@ -93,7 +93,7 @@ interrupt-controller; reg = <0x0 0xfb001000 0x0 0x1000>, <0x0 0xfb002000 0x0 0x2000>, - <0x0 0xfb004000 0x0 0x1000>, + <0x0 0xfb004000 0x0 0x2000>, <0x0 0xfb006000 0x0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi index a9d6d59..47799f5 100644 --- a/arch/arm/boot/dts/axm55xx.dtsi +++ b/arch/arm/boot/dts/axm55xx.dtsi @@ -62,7 +62,7 @@ #address-cells = <0>; interrupt-controller; reg = <0x20 0x01001000 0 0x1000>, - <0x20 0x01002000 0 0x1000>, + <0x20 0x01002000 0 0x2000>, <0x20 0x01004000 0 0x2000>, <0x20 0x01006000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts index 2ccbb57f..c15e7e0 100644 --- a/arch/arm/boot/dts/ecx-2000.dts +++ b/arch/arm/boot/dts/ecx-2000.dts @@ -99,7 +99,7 @@ interrupt-controller; interrupts = <1 9 0xf04>; reg = <0xfff11000 0x1000>, - <0xfff12000 0x1000>, + <0xfff12000 0x2000>, <0xfff14000 0x2000>, <0xfff16000 0x2000>; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index c5c05fd..c139687 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -89,11 +89,11 @@ }; intc: interrupt-controller@00a01000 { - compatible = "arm,cortex-a7-gic"; + compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x00a01000 0x1000>, - <0x00a02000 0x1000>, + <0x00a02000 0x2000>, <0x00a04000 0x2000>, <0x00a06000 0x2000>; }; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 02708ba..e30c83f 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -30,12 +30,12 @@ }; gic: interrupt-controller { - compatible = "arm,cortex-a15-gic"; + compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x02561000 0x0 0x1000>, <0x0 0x02562000 0x0 0x2000>, - <0x0 0x02564000 0x0 0x1000>, + <0x0 0x02564000 0x0 0x2000>, <0x0 0x02566000 0x0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index 9408753..5611a9c 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -124,6 +124,19 @@ }; }; +&qspi { + num-cs = <2>; + status = "okay"; + + qflash0: s25fl128s@0 { + compatible = "spansion,m25p80"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + &enet0 { tbi-handle = <&tbi0>; phy-handle = <&sgmii_phy1c>; diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index a8b148a..907e539 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -142,6 +142,19 @@ }; }; +&qspi { + num-cs = <2>; + status = "okay"; + + qflash0: n25q128a13@0 { + compatible = "n25q128a13", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + &enet0 { tbi-handle = <&tbi1>; phy-handle = <&sgmii_phy2>; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 368e219..9d8d1fe 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -74,17 +74,24 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf00>; - clocks = <&cluster1_clk>; + clocks = <&clockgen 1 0>; }; cpu@f01 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0xf01>; - clocks = <&cluster1_clk>; + clocks = <&clockgen 1 0>; }; }; + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "sysclk"; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, @@ -108,11 +115,11 @@ ranges; gic: interrupt-controller@1400000 { - compatible = "arm,cortex-a7-gic"; + compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x0 0x1401000 0x0 0x1000>, - <0x0 0x1402000 0x0 0x1000>, + <0x0 0x1402000 0x0 0x2000>, <0x0 0x1404000 0x0 0x2000>, <0x0 0x1406000 0x0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; @@ -120,14 +127,14 @@ }; msi1: msi-controller@1570e00 { - compatible = "fsl,1s1021a-msi"; + compatible = "fsl,ls1021a-msi"; reg = <0x0 0x1570e00 0x0 0x8>; msi-controller; interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; }; msi2: msi-controller@1570e08 { - compatible = "fsl,1s1021a-msi"; + compatible = "fsl,ls1021a-msi"; reg = <0x0 0x1570e08 0x0 0x8>; msi-controller; interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; @@ -137,11 +144,12 @@ compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + big-endian; }; dcfg: dcfg@1ee0000 { compatible = "fsl,ls1021a-dcfg", "syscon"; - reg = <0x0 0x1ee0000 0x0 0x10000>; + reg = <0x0 0x1ee0000 0x0 0x1000>; big-endian; }; @@ -163,7 +171,7 @@ <0x0 0x20220520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; dma-coherent; status = "disabled"; }; @@ -214,41 +222,10 @@ }; clockgen: clocking@1ee1000 { - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x0 0x1ee1000 0x10000>; - - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-output-names = "sysclk"; - }; - - cga_pll1: pll@800 { - compatible = "fsl,qoriq-core-pll-2.0"; - #clock-cells = <1>; - reg = <0x800 0x10>; - clocks = <&sysclk>; - clock-output-names = "cga-pll1", "cga-pll1-div2", - "cga-pll1-div4"; - }; - - platform_clk: pll@c00 { - compatible = "fsl,qoriq-core-pll-2.0"; - #clock-cells = <1>; - reg = <0xc00 0x10>; - clocks = <&sysclk>; - clock-output-names = "platform-clk", "platform-clk-div2"; - }; - - cluster1_clk: clk0c0@0 { - compatible = "fsl,qoriq-core-mux-2.0"; - #clock-cells = <0>; - reg = <0x0 0x10>; - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; - clock-output-names = "cluster1-clk"; - }; + compatible = "fsl,ls1021a-clockgen"; + reg = <0x0 0x1ee1000 0x0 0x1000>; + #clock-cells = <2>; + clocks = <&sysclk>; }; dspi0: dspi@2100000 { @@ -258,7 +235,7 @@ reg = <0x0 0x2100000 0x0 0x10000>; interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clock-names = "dspi"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; spi-num-chipselects = <6>; big-endian; status = "disabled"; @@ -271,12 +248,27 @@ reg = <0x0 0x2110000 0x0 0x10000>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; clock-names = "dspi"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; spi-num-chipselects = <6>; big-endian; status = "disabled"; }; + qspi: quadspi@1550000 { + compatible = "fsl,ls1021a-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x1550000 0x0 0x10000>, + <0x0 0x40000000 0x0 0x4000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "qspi_en", "qspi"; + clocks = <&clockgen 4 1>, <&clockgen 4 1>; + big-endian; + amba-base = <0x40000000>; + status = "disabled"; + }; + i2c0: i2c@2180000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; @@ -284,7 +276,7 @@ reg = <0x0 0x2180000 0x0 0x10000>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; status = "disabled"; }; @@ -295,7 +287,7 @@ reg = <0x0 0x2190000 0x0 0x10000>; interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; status = "disabled"; }; @@ -306,7 +298,7 @@ reg = <0x0 0x21a0000 0x0 0x10000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clock-names = "i2c"; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; status = "disabled"; }; @@ -399,7 +391,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2960000 0x0 0x1000>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -408,7 +400,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2970000 0x0 0x1000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -417,7 +409,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2980000 0x0 0x1000>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -426,7 +418,7 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2990000 0x0 0x1000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; @@ -435,16 +427,26 @@ compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x29a0000 0x0 0x1000>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "ipg"; status = "disabled"; }; + ftm0: ftm0@29d0000 { + compatible = "fsl,ls1021a-ftm"; + reg = <0x0 0x29d0000 0x0 0x10000>, + <0x0 0x1ee2140 0x0 0x4>; + reg-names = "ftm", "FlexTimer1"; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + big-endian; + status = "okay"; + }; + wdog0: watchdog@2ad0000 { compatible = "fsl,imx21-wdt"; reg = <0x0 0x2ad0000 0x0 0x10000>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 1>; + clocks = <&clockgen 4 1>; clock-names = "wdog-en"; big-endian; }; @@ -454,8 +456,8 @@ compatible = "fsl,vf610-sai"; reg = <0x0 0x2b50000 0x0 0x10000>; interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 1>, <&platform_clk 1>, - <&platform_clk 1>, <&platform_clk 1>; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 47>, @@ -468,8 +470,8 @@ compatible = "fsl,vf610-sai"; reg = <0x0 0x2b60000 0x0 0x10000>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 1>, <&platform_clk 1>, - <&platform_clk 1>, <&platform_clk 1>; + clocks = <&clockgen 4 1>, <&clockgen 4 1>, + <&clockgen 4 1>, <&clockgen 4 1>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "tx", "rx"; dmas = <&edma0 1 45>, @@ -489,16 +491,31 @@ dma-channels = <32>; big-endian; clock-names = "dmamux0", "dmamux1"; - clocks = <&platform_clk 1>, - <&platform_clk 1>; + clocks = <&clockgen 4 1>, + <&clockgen 4 1>; + }; + + qdma: qdma@8390000 { + compatible = "fsl,ls1021a-qdma"; + reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ + <0x0 0x8389000 0x0 0x1000>, /* Status regs */ + <0x0 0x838a000 0x0 0x2000>; /* Block regs */ + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "qdma-error", "qdma-queue"; + channels = <8>; + queues = <2>; + status-sizes = <64>; + queue-sizes = <64 64>; + big-endian; }; dcu: dcu@2ce0000 { compatible = "fsl,ls1021a-dcu"; reg = <0x0 0x2ce0000 0x0 0x10000>; interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 0>, - <&platform_clk 0>; + clocks = <&clockgen 4 0>, + <&clockgen 4 0>; clock-names = "dcu", "pix"; big-endian; status = "disabled"; @@ -626,6 +643,8 @@ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; snps,quirk-frame-length-adjustment = <0x20>; + configure-gfladj; + dma-coherent; snps,dis_rxdet_inp3_quirk; }; @@ -634,7 +653,9 @@ reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "pme", "aer"; fsl,pcie-scfg = <&scfg 0>; #address-cells = <3>; #size-cells = <2>; @@ -643,7 +664,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi1>; + msi-parent = <&msi1>, <&msi2>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, @@ -657,7 +678,9 @@ reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "pme", "aer"; fsl,pcie-scfg = <&scfg 1>; #address-cells = <3>; #size-cells = <2>; @@ -666,7 +689,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&msi2>; + msi-parent = <&msi1>, <&msi2>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi index 06fdf6c..a349dba 100644 --- a/arch/arm/boot/dts/mt6580.dtsi +++ b/arch/arm/boot/dts/mt6580.dtsi @@ -91,7 +91,7 @@ #interrupt-cells = <3>; interrupt-parent = <&gic>; reg = <0x10211000 0x1000>, - <0x10212000 0x1000>, + <0x10212000 0x2000>, <0x10214000 0x2000>, <0x10216000 0x2000>; }; diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index 88b3cb1..0d6f60a 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -102,7 +102,7 @@ #interrupt-cells = <3>; interrupt-parent = <&gic>; reg = <0x10211000 0x1000>, - <0x10212000 0x1000>, + <0x10212000 0x2000>, <0x10214000 0x2000>, <0x10216000 0x2000>; }; diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi index 52086c8..916c095 100644 --- a/arch/arm/boot/dts/mt8127.dtsi +++ b/arch/arm/boot/dts/mt8127.dtsi @@ -129,7 +129,7 @@ #interrupt-cells = <3>; interrupt-parent = <&gic>; reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x1000>, + <0 0x10212000 0 0x2000>, <0 0x10214000 0 0x2000>, <0 0x10216000 0 0x2000>; }; diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi index 1d7f92b..a97b4ee 100644 --- a/arch/arm/boot/dts/mt8135.dtsi +++ b/arch/arm/boot/dts/mt8135.dtsi @@ -221,7 +221,7 @@ #interrupt-cells = <3>; interrupt-parent = <&gic>; reg = <0 0x10211000 0 0x1000>, - <0 0x10212000 0 0x1000>, + <0 0x10212000 0 0x2000>, <0 0x10214000 0 0x2000>, <0 0x10216000 0 0x2000>; }; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 17ec2e2..559fc54 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1109,7 +1109,7 @@ #address-cells = <0>; reg = <0xffc01000 0x1000>, - <0xffc02000 0x1000>, + <0xffc02000 0x2000>, <0xffc04000 0x2000>, <0xffc06000 0x2000>; interrupts = <GIC_PPI 9 0xf04>; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index ce19604..97f2839 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -791,7 +791,7 @@ gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, + <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 94cf5a1..81e5a44 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -1685,9 +1685,9 @@ }; gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, + <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 300a1bd..cdff588 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -488,7 +488,7 @@ gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, + <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 3c5214c..ba7e7c7 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -613,7 +613,7 @@ gic: interrupt-controller@01c41000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c41000 0x1000>, - <0x01c42000 0x1000>, + <0x01c42000 0x2000>, <0x01c44000 0x2000>, <0x01c46000 0x2000>; interrupt-controller; diff --git a/arch/arm/configs/lsdk.config b/arch/arm/configs/lsdk.config new file mode 100644 index 0000000..efe86c2 --- /dev/null +++ b/arch/arm/configs/lsdk.config @@ -0,0 +1,74 @@ +# general +CONFIG_CHECKPOINT_RESTORE=y + +# virtualization +CONFIG_KVM=y +CONFIG_KVM_ARM_MAX_VCPUS=8 +CONFIG_VHOST_NET=y +CONFIG_BRIDGE=y +CONFIG_TUN=y + +# containers +CONFIG_UNIX_DIAG=y +CONFIG_PACKET_DIAG=y +CONFIG_NETLINK_DIAG=y +CONFIG_OVERLAY_FS=y + +# network and misc +CONFIG_VETH=y +CONFIG_NETFILTER=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_NAT_IPV4=y +CONFIG_NF_NAT_IPV6=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y +CONFIG_MACVLAN=y +CONFIG_MACVTAP=y +CONFIG_VLAN_8021Q=y + +# namespaces +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y + +# cgroups +CONFIG_CPUSETS=y +CGROUP_DEVICE=y +CGROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_MEMCG=y +CONFIG_CGROUP_FREEZER=y + +# iptables +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_IP_NF_FILTER=y +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_IP_VS=y +CONFIG_NETFILTER_XT_MATCH_IPVS=y +CONFIG_POSIX_MQUEUE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_NAT=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y + +# filesystems +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FUSE_FS=y + +# /proc/config.gz +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y diff --git a/arch/arm/configs/lttng.config b/arch/arm/configs/lttng.config new file mode 100644 index 0000000..763250e --- /dev/null +++ b/arch/arm/configs/lttng.config @@ -0,0 +1,21 @@ +# LTTng options +CONFIG_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_NOP_TRACER=y +CONFIG_STACKTRACE=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_TRACEPOINTS=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACE_CLOCK=y +CONFIG_BINARY_PRINTF=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_PERF_EVENTS=y +CONFIG_KPROBES=y +CONFIG_KRETPROBES=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 11f37ed..d296d2b 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -87,6 +87,8 @@ CONFIG_ARCH_EMEV2=y CONFIG_ARCH_R7S72100=y CONFIG_ARCH_R8A73A4=y CONFIG_ARCH_R8A7740=y +CONFIG_ARCH_R8A7743=y +CONFIG_ARCH_R8A7745=y CONFIG_ARCH_R8A7778=y CONFIG_ARCH_R8A7779=y CONFIG_ARCH_R8A7790=y @@ -119,6 +121,7 @@ CONFIG_PCI_KEYSTONE=y CONFIG_PCI_MSI=y CONFIG_PCI_MVEBU=y CONFIG_PCI_TEGRA=y +CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_RCAR_GEN2=y CONFIG_PCIE_RCAR=y CONFIG_PCIEPORTBUS=y @@ -132,7 +135,7 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_KEXEC=y CONFIG_EFI=y CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_STAT_DETAILS=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_POWERSAVE=m CONFIG_CPU_FREQ_GOV_USERSPACE=m @@ -172,7 +175,13 @@ CONFIG_CAN_AT91=m CONFIG_CAN_RCAR=m CONFIG_CAN_XILINXCAN=y CONFIG_CAN_MCP251X=y +CONFIG_CAN_FLEXCAN=y CONFIG_NET_DSA_BCM_SF2=m +CONFIG_B53=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m CONFIG_CAN_SUN4I=y CONFIG_BT=m CONFIG_BT_MRVL=m @@ -188,23 +197,33 @@ CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=64 CONFIG_OMAP_OCP2SCP=y CONFIG_SIMPLE_PM_BUS=y -CONFIG_SUNXI_RSB=m +CONFIG_SUNXI_RSB=y CONFIG_MTD=y CONFIG_MTD_CMDLINE_PARTS=y CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y CONFIG_MTD_M25P80=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_SST25L=y CONFIG_MTD_NAND=y CONFIG_MTD_NAND_DENALI_DT=y CONFIG_MTD_NAND_ATMEL=y CONFIG_MTD_NAND_BRCMNAND=y CONFIG_MTD_NAND_VF610_NFC=y CONFIG_MTD_NAND_DAVINCI=y +CONFIG_MTD_NAND_FSL_IFC=y CONFIG_MTD_SPI_NOR=y CONFIG_SPI_FSL_QUADSPI=m CONFIG_MTD_UBI=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_BLK_DEV_RAM_SIZE=262144 CONFIG_VIRTIO_BLK=y CONFIG_AD525X_DPOT=y CONFIG_AD525X_DPOT_I2C=y @@ -226,6 +245,9 @@ CONFIG_AHCI_ST=y CONFIG_AHCI_IMX=y CONFIG_AHCI_SUNXI=y CONFIG_AHCI_TEGRA=y +CONFIG_AHCI_QORIQ=y +CONFIG_SATA_SIL24=y +CONFIG_CHR_DEV_SG=y CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y CONFIG_SATA_RCAR=y @@ -235,6 +257,7 @@ CONFIG_HIX5HD2_GMAC=y CONFIG_SUN4I_EMAC=y CONFIG_MACB=y CONFIG_BCMGENET=m +CONFIG_BGMAC_BCMA=y CONFIG_SYSTEMPORT=m CONFIG_NET_CALXEDA_XGMAC=y CONFIG_GIANFAR=y @@ -247,7 +270,8 @@ CONFIG_R8169=y CONFIG_SH_ETH=y CONFIG_SMSC911X=y CONFIG_STMMAC_ETH=y -CONFIG_SYNOPSYS_DWC_ETH_QOS=y +CONFIG_STMMAC_PLATFORM=y +CONFIG_DWMAC_DWC_QOS_ETH=y CONFIG_TI_CPSW=y CONFIG_XILINX_EMACLITE=y CONFIG_AT803X_PHY=y @@ -257,6 +281,7 @@ CONFIG_BROADCOM_PHY=y CONFIG_ICPLUS_PHY=y CONFIG_REALTEK_PHY=y CONFIG_MICREL_PHY=y +CONFIG_NATIONAL_PHY=y CONFIG_FIXED_PHY=y CONFIG_USB_PEGASUS=y CONFIG_USB_RTL8152=m @@ -290,7 +315,6 @@ CONFIG_TOUCHSCREEN_WM97XX=m CONFIG_INPUT_MISC=y CONFIG_INPUT_MAX77693_HAPTIC=m CONFIG_INPUT_MAX8997_HAPTIC=m -CONFIG_INPUT_MPU3050=y CONFIG_INPUT_AXP20X_PEK=m CONFIG_INPUT_ADXL34X=m CONFIG_SERIO_AMBAKMI=y @@ -351,7 +375,7 @@ CONFIG_I2C_DIGICOLOR=m CONFIG_I2C_EMEV2=m CONFIG_I2C_GPIO=m CONFIG_I2C_EXYNOS5=y -CONFIG_I2C_IMX=m +CONFIG_I2C_IMX=y CONFIG_I2C_MV64XXX=y CONFIG_I2C_RIIC=y CONFIG_I2C_RK3X=y @@ -404,7 +428,6 @@ CONFIG_PINCTRL_MSM8X74=y CONFIG_PINCTRL_MSM8916=y CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_PINCTRL_QCOM_SSBI_PMIC=y -CONFIG_GPIO_SYSFS=y CONFIG_GPIO_GENERIC_PLATFORM=y CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y @@ -450,7 +473,6 @@ CONFIG_RCAR_THERMAL=y CONFIG_ARMADA_THERMAL=y CONFIG_DAVINCI_WATCHDOG=m CONFIG_EXYNOS_THERMAL=m -CONFIG_ST_THERMAL_SYSCFG=y CONFIG_ST_THERMAL_MEMMAP=y CONFIG_WATCHDOG=y CONFIG_DA9063_WATCHDOG=m @@ -467,6 +489,7 @@ CONFIG_MESON_WATCHDOG=y CONFIG_DW_WATCHDOG=y CONFIG_DIGICOLOR_WATCHDOG=y CONFIG_BCM2835_WDT=y +CONFIG_BCM47XX_WDT=y CONFIG_BCM7038_WDT=m CONFIG_BCM_KONA_WDT=y CONFIG_MFD_ACT8945A=y @@ -475,9 +498,10 @@ CONFIG_MFD_AS3722=y CONFIG_MFD_ATMEL_FLEXCOM=y CONFIG_MFD_ATMEL_HLCDC=m CONFIG_MFD_BCM590XX=y +CONFIG_MFD_AC100=y CONFIG_MFD_AXP20X=y -CONFIG_MFD_AXP20X_I2C=m -CONFIG_MFD_AXP20X_RSB=m +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_AXP20X_RSB=y CONFIG_MFD_CROS_EC=m CONFIG_MFD_CROS_EC_I2C=m CONFIG_MFD_CROS_EC_SPI=m @@ -489,7 +513,7 @@ CONFIG_MFD_MAX8907=y CONFIG_MFD_MAX8997=y CONFIG_MFD_MAX8998=y CONFIG_MFD_RK808=y -CONFIG_MFD_PM8921_CORE=y +CONFIG_MFD_PM8XXX=y CONFIG_MFD_QCOM_RPM=y CONFIG_MFD_SPMI_PMIC=y CONFIG_MFD_SEC_CORE=y @@ -506,7 +530,7 @@ CONFIG_REGULATOR_ACT8865=y CONFIG_REGULATOR_ANATOP=y CONFIG_REGULATOR_AS3711=y CONFIG_REGULATOR_AS3722=y -CONFIG_REGULATOR_AXP20X=m +CONFIG_REGULATOR_AXP20X=y CONFIG_REGULATOR_BCM590XX=y CONFIG_REGULATOR_DA9210=y CONFIG_REGULATOR_FAN53555=y @@ -561,7 +585,10 @@ CONFIG_VIDEO_EXYNOS4_FIMC_IS=m CONFIG_V4L_MEM2MEM_DRIVERS=y CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m CONFIG_VIDEO_SAMSUNG_S5P_MFC=m +CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m CONFIG_VIDEO_STI_BDISP=m +CONFIG_VIDEO_STI_HVA=m +CONFIG_VIDEO_STI_DELTA=m CONFIG_VIDEO_RENESAS_JPU=m CONFIG_VIDEO_RENESAS_VSP1=m CONFIG_V4L_TEST_DRIVERS=y @@ -572,6 +599,7 @@ CONFIG_DRM=y CONFIG_DRM_I2C_ADV7511=m # CONFIG_DRM_I2C_CH7006 is not set # CONFIG_DRM_I2C_SIL164 is not set +CONFIG_DRM_DUMB_VGA_DAC=m CONFIG_DRM_NXP_PTN3460=m CONFIG_DRM_PARADE_PS8622=m CONFIG_DRM_NOUVEAU=m @@ -582,10 +610,10 @@ CONFIG_DRM_EXYNOS_DPI=y CONFIG_DRM_EXYNOS_DSI=y CONFIG_DRM_EXYNOS_HDMI=y CONFIG_DRM_ROCKCHIP=m -CONFIG_ROCKCHIP_ANALOGIX_DP=m -CONFIG_ROCKCHIP_DW_HDMI=m -CONFIG_ROCKCHIP_DW_MIPI_DSI=m -CONFIG_ROCKCHIP_INNO_HDMI=m +CONFIG_ROCKCHIP_ANALOGIX_DP=y +CONFIG_ROCKCHIP_DW_HDMI=y +CONFIG_ROCKCHIP_DW_MIPI_DSI=y +CONFIG_ROCKCHIP_INNO_HDMI=y CONFIG_DRM_ATMEL_HLCDC=m CONFIG_DRM_RCAR_DU=m CONFIG_DRM_RCAR_HDMI=y @@ -597,6 +625,9 @@ CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0=m CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_STI=m CONFIG_DRM_VC4=y +CONFIG_DRM_FSL_DCU=y +CONFIG_DRM_SII902X=y +CONFIG_LOGO=y CONFIG_FB_ARMCLCD=y CONFIG_FB_EFI=y CONFIG_FB_WM8505=y @@ -649,6 +680,9 @@ CONFIG_SND_SOC_AK4642=m CONFIG_SND_SOC_SGTL5000=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8978=m +CONFIG_SND_SOC_STI=m +CONFIG_SND_SOC_STI_SAS=m +CONFIG_SND_SIMPLE_CARD=m CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_MVEBU=y @@ -693,7 +727,7 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_OF_ARASAN=y CONFIG_MMC_SDHCI_OF_AT91=y -CONFIG_MMC_SDHCI_OF_ESDHC=m +CONFIG_MMC_SDHCI_OF_ESDHC=y CONFIG_MMC_SDHCI_ESDHC_IMX=y CONFIG_MMC_SDHCI_DOVE=y CONFIG_MMC_SDHCI_TEGRA=y @@ -716,6 +750,7 @@ CONFIG_MMC_DW_EXYNOS=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SH_MMCIF=y CONFIG_MMC_SUNXI=y +CONFIG_MMC_BCM2835=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLASS_FLASH=m @@ -734,12 +769,15 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LEDS_TRIGGER_CAMERA=y CONFIG_EDAC=y -CONFIG_EDAC_MM_EDAC=y CONFIG_EDAC_HIGHBANK_MC=y CONFIG_EDAC_HIGHBANK_L2=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_AC100=y CONFIG_RTC_DRV_AS3722=y CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_DS3232=y +CONFIG_RTC_DRV_PCF2127=y +CONFIG_RTC_DRV_PCF85263=y CONFIG_RTC_DRV_HYM8563=m CONFIG_RTC_DRV_MAX8907=y CONFIG_RTC_DRV_MAX8998=m @@ -790,6 +828,7 @@ CONFIG_DMA_OMAP=y CONFIG_QCOM_BAM_DMA=y CONFIG_XILINX_DMA=y CONFIG_DMA_SUN6I=y +CONFIG_ST_FDMA=m CONFIG_STAGING=y CONFIG_SENSORS_ISL29018=y CONFIG_SENSORS_ISL29028=y @@ -798,6 +837,10 @@ CONFIG_KEYBOARD_NVEC=y CONFIG_SERIO_NVEC_PS2=y CONFIG_NVEC_POWER=y CONFIG_NVEC_PAZ00=y +CONFIG_BCMA=y +CONFIG_BCMA_HOST_SOC=y +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y CONFIG_QCOM_GSBI=y CONFIG_QCOM_PM=y CONFIG_QCOM_SMEM=y @@ -808,6 +851,7 @@ CONFIG_QCOM_SMSM=y CONFIG_QCOM_WCNSS_CTRL=m CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_COMMON_CLK_QCOM=y +CONFIG_QCOM_CLK_RPM=y CONFIG_CHROME_PLATFORMS=y CONFIG_STAGING_BOARD=y CONFIG_CROS_EC_CHARDEV=m @@ -823,21 +867,26 @@ CONFIG_HWSPINLOCK_QCOM=y CONFIG_ROCKCHIP_IOMMU=y CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_SMMU=y +CONFIG_REMOTEPROC=m +CONFIG_ST_REMOTEPROC=m CONFIG_PM_DEVFREQ=y CONFIG_ARM_TEGRA_DEVFREQ=m CONFIG_MEMORY=y CONFIG_EXTCON=y CONFIG_TI_AEMIF=y CONFIG_IIO=y +CONFIG_IIO_SW_TRIGGER=y CONFIG_AT91_ADC=m CONFIG_AT91_SAMA5D2_ADC=m CONFIG_BERLIN2_ADC=m CONFIG_EXYNOS_ADC=m CONFIG_VF610_ADC=m CONFIG_XILINX_XADC=y +CONFIG_MPU3050_I2C=y CONFIG_CM36651=m CONFIG_AK8975=y CONFIG_RASPBERRYPI_POWER=y +CONFIG_IIO_HRTIMER_TRIGGER=y CONFIG_PWM=y CONFIG_PWM_ATMEL=m CONFIG_PWM_ATMEL_HLCDC_PWM=m @@ -862,9 +911,7 @@ CONFIG_PHY_ROCKCHIP_DP=m CONFIG_PHY_ROCKCHIP_USB=m CONFIG_PHY_QCOM_APQ8064_SATA=m CONFIG_PHY_MIPHY28LP=y -CONFIG_PHY_MIPHY365X=y CONFIG_PHY_RCAR_GEN2=m -CONFIG_PHY_STIH41X_USB=y CONFIG_PHY_STIH407_USB=y CONFIG_PHY_SUN4I_USB=y CONFIG_PHY_SUN9I_USB=y @@ -877,6 +924,8 @@ CONFIG_BCM2835_MBOX=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_EFI_VARS=m CONFIG_EFI_CAPSULE_LOADER=m +CONFIG_BCM47XX_NVRAM=y +CONFIG_BCM47XX_SPROM=y CONFIG_EXT4_FS=y CONFIG_AUTOFS4_FS=y CONFIG_MSDOS_FS=y @@ -888,6 +937,10 @@ CONFIG_TMPFS=y CONFIG_SQUASHFS=y CONFIG_SQUASHFS_LZO=y CONFIG_SQUASHFS_XZ=y +CONFIG_PSTORE=y +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=y CONFIG_NFS_FS=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y @@ -918,12 +971,29 @@ CONFIG_CRYPTO_SHA512_ARM=m CONFIG_CRYPTO_AES_ARM=m CONFIG_CRYPTO_AES_ARM_BS=m CONFIG_CRYPTO_AES_ARM_CE=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_CRC32_ARM_CE=m +CONFIG_CRYPTO_CRCT10DIF_ARM_CE=m CONFIG_CRYPTO_GHASH_ARM_CE=m CONFIG_CRYPTO_DEV_ATMEL_AES=m CONFIG_CRYPTO_DEV_ATMEL_TDES=m CONFIG_CRYPTO_DEV_ATMEL_SHA=m +CONFIG_CRYPTO_DEV_FSL_CAAM=m CONFIG_VIDEO_VIVID=m CONFIG_VIRTIO=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_PCI_LEGACY=y CONFIG_VIRTIO_MMIO=y +CONFIG_VIRTUALIZATION=y +CONFIG_VHOST_NET=y +#flextimer +CONFIG_LS_SOC_DRIVERS=y +CONFIG_FTM_ALARM=y +# DPAA 1 +CONFIG_FSL_SDK_DPA=y +CONFIG_FSL_SDK_FMAN=y +CONFIG_FSL_SDK_DPAA_ETH=y +# Ethernet PHYs +CONFIG_VITESSE_PHY=y +CONFIG_AQUANTIA_PHY=y +CONFIG_FSL_XGMAC_MDIO=y diff --git a/arch/arm/configs/multi_v7_lpae.config b/arch/arm/configs/multi_v7_lpae.config new file mode 100644 index 0000000..cd13d2d --- /dev/null +++ b/arch/arm/configs/multi_v7_lpae.config @@ -0,0 +1,2 @@ +# Support for the Large Physical Address Extension +CONFIG_ARM_LPAE=y diff --git a/arch/arm/configs/multi_v8.config b/arch/arm/configs/multi_v8.config new file mode 100644 index 0000000..d76a316 --- /dev/null +++ b/arch/arm/configs/multi_v8.config @@ -0,0 +1,25 @@ +# ppfe +CONFIG_FSL_PPFE=y +# DPAA 1 +CONFIG_FSL_SDK_DPA=y +# network +CONFIG_BRIDGE=m +CONFIG_MACVLAN=y +CONFIG_FSL_SDK_FMAN=y +CONFIG_FMAN_ARM=y +CONFIG_FSL_SDK_DPAA_ETH=y +CONFIG_INET_ESP=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +# mdio +CONFIG_FSL_XGMAC_MDIO=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +# phy +CONFIG_AQUANTIA_PHY=y +CONFIG_VITESSE_PHY=y +# NVMe +CONFIG_BLK_DEV_NVME=y +# vfio +CONFIG_VFIO=y +CONFIG_VFIO_PCI=y +CONFIG_VFIO_FSL_MC=y diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h index b1ce037..1445b0c 100644 --- a/arch/arm/include/asm/delay.h +++ b/arch/arm/include/asm/delay.h @@ -57,6 +57,22 @@ extern void __bad_udelay(void); __const_udelay((n) * UDELAY_MULT)) : \ __udelay(n)) +#define spin_event_timeout(condition, timeout, delay) \ +({ \ + typeof(condition) __ret; \ + int i = 0; \ + while (!(__ret = (condition)) && (i++ < timeout)) { \ + if (delay) \ + udelay(delay); \ + else \ + cpu_relax(); \ + udelay(1); \ + } \ + if (!__ret) \ + __ret = (condition); \ + __ret; \ +}) + /* Loop-based definitions for assembly code. */ extern void __loop_delay(unsigned long loops); extern void __loop_udelay(unsigned long usecs); diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 021692c..172a4f2 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -129,6 +129,7 @@ static inline u32 __raw_readl(const volatile void __iomem *addr) #define MT_DEVICE_NONSHARED 1 #define MT_DEVICE_CACHED 2 #define MT_DEVICE_WC 3 +#define MT_MEMORY_RW_NS 4 /* * types 4 onwards can be found in asm/mach/map.h and are undefined * for ioremap @@ -220,6 +221,34 @@ extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr); #endif #endif +/* access ports */ +#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr)) +#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr)) + +#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr)) +#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr)) + +#define setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr)) +#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr)) + +/* Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single read-modify-write. These + * macros can also be used to set a multiple-bit bit pattern using a mask, + * by specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrsetbits_be32(addr, clear, set) \ + iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr)) +#define clrsetbits_le32(addr, clear, set) \ + iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr)) +#define clrsetbits_be16(addr, clear, set) \ + iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr)) +#define clrsetbits_le16(addr, clear, set) \ + iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr)) +#define clrsetbits_8(addr, clear, set) \ + iowrite8((ioread8(addr) & ~(clear)) | (set), (addr)) + /* * IO port access primitives * ------------------------- @@ -408,6 +437,8 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size); #define ioremap_wc ioremap_wc #define ioremap_wt ioremap_wc +void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size); + void iounmap(volatile void __iomem *iomem_cookie); #define iounmap iounmap diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index 9b7c328..27f3df7 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h @@ -21,9 +21,9 @@ struct map_desc { unsigned int type; }; -/* types 0-3 are defined in asm/io.h */ +/* types 0-4 are defined in asm/io.h */ enum { - MT_UNCACHED = 4, + MT_UNCACHED = 5, MT_CACHECLEAN, MT_MINICLEAN, MT_LOW_VECTORS, diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index a8d656d..4ab57b3 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h @@ -118,6 +118,13 @@ extern pgprot_t pgprot_s2_device; #define pgprot_noncached(prot) \ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED) +#define pgprot_cached(prot) \ + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED) + +#define pgprot_cached_ns(prot) \ + __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \ + L_PTE_MT_DEV_NONSHARED) + #define pgprot_writecombine(prot) \ __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE) diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index 2f0e077..d2f4869 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c @@ -11,6 +11,8 @@ #include <linux/slab.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/of_irq.h> +#include <linux/pcieport_if.h> #include <asm/mach-types.h> #include <asm/mach/map.h> @@ -64,6 +66,47 @@ void pcibios_report_status(u_int status_mask, int warn) } /* + * Check device tree if the service interrupts are there + */ +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask) +{ + int ret, count = 0; + struct device_node *np = NULL; + + if (dev->bus->dev.of_node) + np = dev->bus->dev.of_node; + + if (np == NULL) + return 0; + + if (!IS_ENABLED(CONFIG_OF_IRQ)) + return 0; + + /* If root port doesn't support MSI/MSI-X/INTx in RC mode, + * request irq for aer + */ + if (mask & PCIE_PORT_SERVICE_AER) { + ret = of_irq_get_byname(np, "aer"); + if (ret > 0) { + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret; + count++; + } + } + + if (mask & PCIE_PORT_SERVICE_PME) { + ret = of_irq_get_byname(np, "pme"); + if (ret > 0) { + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret; + count++; + } + } + + /* TODO: add more service interrupts if there it is in the device tree*/ + + return count; +} + +/* * We don't use this to fix the device, but initialisation of it. * It's not the correct use for this, but it works. * Note that the arbiter/ISA bridge appears to be buggy, specifically in diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index ab77100..9b5f446 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -2392,6 +2392,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, set_dma_ops(dev, dma_ops); } +EXPORT_SYMBOL(arch_setup_dma_ops); void arch_teardown_dma_ops(struct device *dev) { diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index ff0eed2..2f2f426 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -398,6 +398,13 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size) } EXPORT_SYMBOL(ioremap_wc); +void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size) +{ + return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RW_NS, + __builtin_return_address(0)); +} +EXPORT_SYMBOL(ioremap_cache_ns); + /* * Remap an arbitrary physical address space into the kernel virtual * address space as memory. Needed when the kernel wants to execute diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index f7c7413..4a2fb70 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c @@ -313,6 +313,13 @@ static struct mem_type mem_types[] __ro_after_init = { .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, .domain = DOMAIN_KERNEL, }, + [MT_MEMORY_RW_NS] = { + .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | + L_PTE_XN, + .prot_l1 = PMD_TYPE_TABLE, + .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN, + .domain = DOMAIN_KERNEL, + }, [MT_ROM] = { .prot_sect = PMD_TYPE_SECT, .domain = DOMAIN_KERNEL, @@ -644,6 +651,7 @@ static void __init build_mem_type_table(void) } kern_pgprot |= PTE_EXT_AF; vecs_pgprot |= PTE_EXT_AF; + mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte; /* * Set PXN for user mappings @@ -672,6 +680,7 @@ static void __init build_mem_type_table(void) mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; + mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd; mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; mem_types[MT_ROM].prot_sect |= cp->pmd; |