diff options
Diffstat (limited to 'arch/tile/include/uapi/asm')
-rw-r--r-- | arch/tile/include/uapi/asm/auxvec.h | 3 | ||||
-rw-r--r-- | arch/tile/include/uapi/asm/cachectl.h | 4 |
2 files changed, 4 insertions, 3 deletions
diff --git a/arch/tile/include/uapi/asm/auxvec.h b/arch/tile/include/uapi/asm/auxvec.h index 1d393ed..c93e927 100644 --- a/arch/tile/include/uapi/asm/auxvec.h +++ b/arch/tile/include/uapi/asm/auxvec.h @@ -15,6 +15,7 @@ #ifndef _ASM_TILE_AUXVEC_H #define _ASM_TILE_AUXVEC_H -/* No extensions to auxvec */ +/* The vDSO location. */ +#define AT_SYSINFO_EHDR 33 #endif /* _ASM_TILE_AUXVEC_H */ diff --git a/arch/tile/include/uapi/asm/cachectl.h b/arch/tile/include/uapi/asm/cachectl.h index af4c9f9..572ddca 100644 --- a/arch/tile/include/uapi/asm/cachectl.h +++ b/arch/tile/include/uapi/asm/cachectl.h @@ -29,8 +29,8 @@ * to honor the arguments at some point.) * * Flush and invalidation of memory can normally be performed with the - * __insn_flush(), __insn_inv(), and __insn_finv() instructions from - * userspace. The DCACHE option to the system call allows userspace + * __insn_flush() and __insn_finv() instructions from userspace. + * The DCACHE option to the system call allows userspace * to flush the entire L1+L2 data cache from the core. In this case, * the address and length arguments are not used. The DCACHE flush is * restricted to the current core, not all cores in the address space. |