diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c | 126 |
1 files changed, 57 insertions, 69 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c index 045d256..750183f 100644 --- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c +++ b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c @@ -32,36 +32,74 @@ struct nv50_dmaeng_priv { struct nouveau_dmaeng base; }; -struct nv50_dmaobj_priv { - struct nouveau_dmaobj base; -}; - static int nv50_dmaobj_bind(struct nouveau_dmaeng *dmaeng, struct nouveau_object *parent, struct nouveau_dmaobj *dmaobj, struct nouveau_gpuobj **pgpuobj) { - u32 flags = nv_mclass(dmaobj); + u32 flags0 = nv_mclass(dmaobj); + u32 flags5 = 0x00000000; int ret; + if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { + switch (nv_mclass(parent->parent)) { + case NV50_CHANNEL_DMA_CLASS: + case NV84_CHANNEL_DMA_CLASS: + case NV50_CHANNEL_IND_CLASS: + case NV84_CHANNEL_IND_CLASS: + case NV50_DISP_MAST_CLASS: + case NV84_DISP_MAST_CLASS: + case NV94_DISP_MAST_CLASS: + case NVA0_DISP_MAST_CLASS: + case NVA3_DISP_MAST_CLASS: + case NV50_DISP_SYNC_CLASS: + case NV84_DISP_SYNC_CLASS: + case NV94_DISP_SYNC_CLASS: + case NVA0_DISP_SYNC_CLASS: + case NVA3_DISP_SYNC_CLASS: + case NV50_DISP_OVLY_CLASS: + case NV84_DISP_OVLY_CLASS: + case NV94_DISP_OVLY_CLASS: + case NVA0_DISP_OVLY_CLASS: + case NVA3_DISP_OVLY_CLASS: + break; + default: + return -EINVAL; + } + } + + if (!(dmaobj->conf0 & NV50_DMA_CONF0_ENABLE)) { + if (dmaobj->target == NV_MEM_TARGET_VM) { + dmaobj->conf0 = NV50_DMA_CONF0_PRIV_VM; + dmaobj->conf0 |= NV50_DMA_CONF0_PART_VM; + dmaobj->conf0 |= NV50_DMA_CONF0_COMP_VM; + dmaobj->conf0 |= NV50_DMA_CONF0_TYPE_VM; + } else { + dmaobj->conf0 = NV50_DMA_CONF0_PRIV_US; + dmaobj->conf0 |= NV50_DMA_CONF0_PART_256; + dmaobj->conf0 |= NV50_DMA_CONF0_COMP_NONE; + dmaobj->conf0 |= NV50_DMA_CONF0_TYPE_LINEAR; + } + } + + flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_COMP) << 22; + flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_TYPE) << 22; + flags0 |= (dmaobj->conf0 & NV50_DMA_CONF0_PRIV); + flags5 |= (dmaobj->conf0 & NV50_DMA_CONF0_PART); + switch (dmaobj->target) { case NV_MEM_TARGET_VM: - flags |= 0x00000000; - flags |= 0x60000000; /* COMPRESSION_USEVM */ - flags |= 0x1fc00000; /* STORAGE_TYPE_USEVM */ + flags0 |= 0x00000000; break; case NV_MEM_TARGET_VRAM: - flags |= 0x00010000; - flags |= 0x00100000; /* ACCESSUS_USER_SYSTEM */ + flags0 |= 0x00010000; break; case NV_MEM_TARGET_PCI: - flags |= 0x00020000; - flags |= 0x00100000; /* ACCESSUS_USER_SYSTEM */ + flags0 |= 0x00020000; break; case NV_MEM_TARGET_PCI_NOSNOOP: - flags |= 0x00030000; - flags |= 0x00100000; /* ACCESSUS_USER_SYSTEM */ + flags0 |= 0x00030000; break; default: return -EINVAL; @@ -71,79 +109,29 @@ nv50_dmaobj_bind(struct nouveau_dmaeng *dmaeng, case NV_MEM_ACCESS_VM: break; case NV_MEM_ACCESS_RO: - flags |= 0x00040000; + flags0 |= 0x00040000; break; case NV_MEM_ACCESS_WO: case NV_MEM_ACCESS_RW: - flags |= 0x00080000; + flags0 |= 0x00080000; break; } ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); if (ret == 0) { - nv_wo32(*pgpuobj, 0x00, flags); + nv_wo32(*pgpuobj, 0x00, flags0); nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->limit)); nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->start)); nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->limit) << 24 | upper_32_bits(dmaobj->start)); nv_wo32(*pgpuobj, 0x10, 0x00000000); - nv_wo32(*pgpuobj, 0x14, 0x00000000); + nv_wo32(*pgpuobj, 0x14, flags5); } return ret; } static int -nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) -{ - struct nouveau_dmaeng *dmaeng = (void *)engine; - struct nv50_dmaobj_priv *dmaobj; - struct nouveau_gpuobj *gpuobj; - int ret; - - ret = nouveau_dmaobj_create(parent, engine, oclass, - data, size, &dmaobj); - *pobject = nv_object(dmaobj); - if (ret) - return ret; - - switch (nv_mclass(parent)) { - case NV_DEVICE_CLASS: - break; - case NV50_CHANNEL_DMA_CLASS: - case NV84_CHANNEL_DMA_CLASS: - case NV50_CHANNEL_IND_CLASS: - case NV84_CHANNEL_IND_CLASS: - ret = dmaeng->bind(dmaeng, *pobject, &dmaobj->base, &gpuobj); - nouveau_object_ref(NULL, pobject); - *pobject = nv_object(gpuobj); - break; - default: - return -EINVAL; - } - - return ret; -} - -static struct nouveau_ofuncs -nv50_dmaobj_ofuncs = { - .ctor = nv50_dmaobj_ctor, - .dtor = _nouveau_dmaobj_dtor, - .init = _nouveau_dmaobj_init, - .fini = _nouveau_dmaobj_fini, -}; - -static struct nouveau_oclass -nv50_dmaobj_sclass[] = { - { 0x0002, &nv50_dmaobj_ofuncs }, - { 0x0003, &nv50_dmaobj_ofuncs }, - { 0x003d, &nv50_dmaobj_ofuncs }, - {} -}; - -static int nv50_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) @@ -156,7 +144,7 @@ nv50_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine, if (ret) return ret; - priv->base.base.sclass = nv50_dmaobj_sclass; + nv_engine(priv)->sclass = nouveau_dmaobj_sclass; priv->base.bind = nv50_dmaobj_bind; return 0; } |