diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau')
60 files changed, 1038 insertions, 1131 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h index 2b0fe0e..9571710 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h @@ -220,5 +220,22 @@ #define nva3_clk_info gt215_clk_info #define nva3_pll_info gt215_pll_info #define nouveau_ibus nvkm_ibus +#define nouveau_memx nvkm_memx +#define nouveau_memx_block nvkm_memx_block +#define nouveau_memx_unblock nvkm_memx_unblock +#define nouveau_memx_train nvkm_memx_train +#define nouveau_memx_train_result nvkm_memx_train_result +#define nouveau_memx_wait_vblank nvkm_memx_wait_vblank +#define nouveau_memx_rd32 nvkm_memx_rd32 +#define nouveau_memx_wr32 nvkm_memx_wr32 +#define nouveau_memx_wait nvkm_memx_wait +#define nouveau_memx_init nvkm_memx_init +#define nouveau_memx_fini nvkm_memx_fini +#define nouveau_memx_nsec nvkm_memx_nsec +#define nouveau_ltc nvkm_ltc +#define nouveau_pmu nvkm_pmu +#define nouveau_fb nvkm_fb +#define nouveau_fb_tile nvkm_fb_tile +#define nvc0_pte_storage_type_map gf100_pte_storage_type_map #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h index b6a2100..16da56c 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h @@ -1,9 +1,6 @@ -#ifndef __NOUVEAU_FB_H__ -#define __NOUVEAU_FB_H__ - +#ifndef __NVKM_FB_H__ +#define __NVKM_FB_H__ #include <core/subdev.h> -#include <core/device.h> -#include <core/mm.h> #include <subdev/mmu.h> @@ -24,14 +21,14 @@ #define NV_MEM_TYPE_VM 0x7f #define NV_MEM_COMP_VM 0x03 -struct nouveau_mem { +struct nvkm_mem { struct drm_device *dev; - struct nouveau_vma bar_vma; - struct nouveau_vma vma[2]; + struct nvkm_vma bar_vma; + struct nvkm_vma vma[2]; u8 page_shift; - struct nouveau_mm_node *tag; + struct nvkm_mm_node *tag; struct list_head regions; dma_addr_t *pages; u32 memtype; @@ -40,85 +37,83 @@ struct nouveau_mem { struct sg_table *sg; }; -struct nouveau_fb_tile { - struct nouveau_mm_node *tag; +struct nvkm_fb_tile { + struct nvkm_mm_node *tag; u32 addr; u32 limit; u32 pitch; u32 zcomp; }; -struct nouveau_fb { - struct nouveau_subdev base; +struct nvkm_fb { + struct nvkm_subdev base; - bool (*memtype_valid)(struct nouveau_fb *, u32 memtype); + bool (*memtype_valid)(struct nvkm_fb *, u32 memtype); - struct nouveau_ram *ram; + struct nvkm_ram *ram; - struct nouveau_mm vram; - struct nouveau_mm tags; + struct nvkm_mm vram; + struct nvkm_mm tags; struct { - struct nouveau_fb_tile region[16]; + struct nvkm_fb_tile region[16]; int regions; - void (*init)(struct nouveau_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nouveau_fb_tile *); - void (*comp)(struct nouveau_fb *, int i, u32 size, u32 flags, - struct nouveau_fb_tile *); - void (*fini)(struct nouveau_fb *, int i, - struct nouveau_fb_tile *); - void (*prog)(struct nouveau_fb *, int i, - struct nouveau_fb_tile *); + void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); + void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags, + struct nvkm_fb_tile *); + void (*fini)(struct nvkm_fb *, int i, struct nvkm_fb_tile *); + void (*prog)(struct nvkm_fb *, int i, struct nvkm_fb_tile *); } tile; }; -static inline struct nouveau_fb * -nouveau_fb(void *obj) +static inline struct nvkm_fb * +nvkm_fb(void *obj) { /* fbram uses this before device subdev pointer is valid */ if (nv_iclass(obj, NV_SUBDEV_CLASS) && nv_subidx(obj) == NVDEV_SUBDEV_FB) return obj; - return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_FB); + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_FB); } -extern struct nouveau_oclass *nv04_fb_oclass; -extern struct nouveau_oclass *nv10_fb_oclass; -extern struct nouveau_oclass *nv1a_fb_oclass; -extern struct nouveau_oclass *nv20_fb_oclass; -extern struct nouveau_oclass *nv25_fb_oclass; -extern struct nouveau_oclass *nv30_fb_oclass; -extern struct nouveau_oclass *nv35_fb_oclass; -extern struct nouveau_oclass *nv36_fb_oclass; -extern struct nouveau_oclass *nv40_fb_oclass; -extern struct nouveau_oclass *nv41_fb_oclass; -extern struct nouveau_oclass *nv44_fb_oclass; -extern struct nouveau_oclass *nv46_fb_oclass; -extern struct nouveau_oclass *nv47_fb_oclass; -extern struct nouveau_oclass *nv49_fb_oclass; -extern struct nouveau_oclass *nv4e_fb_oclass; -extern struct nouveau_oclass *nv50_fb_oclass; -extern struct nouveau_oclass *nv84_fb_oclass; -extern struct nouveau_oclass *nva3_fb_oclass; -extern struct nouveau_oclass *nvaa_fb_oclass; -extern struct nouveau_oclass *nvaf_fb_oclass; -extern struct nouveau_oclass *nvc0_fb_oclass; -extern struct nouveau_oclass *nve0_fb_oclass; -extern struct nouveau_oclass *gk20a_fb_oclass; -extern struct nouveau_oclass *gm107_fb_oclass; +extern struct nvkm_oclass *nv04_fb_oclass; +extern struct nvkm_oclass *nv10_fb_oclass; +extern struct nvkm_oclass *nv1a_fb_oclass; +extern struct nvkm_oclass *nv20_fb_oclass; +extern struct nvkm_oclass *nv25_fb_oclass; +extern struct nvkm_oclass *nv30_fb_oclass; +extern struct nvkm_oclass *nv35_fb_oclass; +extern struct nvkm_oclass *nv36_fb_oclass; +extern struct nvkm_oclass *nv40_fb_oclass; +extern struct nvkm_oclass *nv41_fb_oclass; +extern struct nvkm_oclass *nv44_fb_oclass; +extern struct nvkm_oclass *nv46_fb_oclass; +extern struct nvkm_oclass *nv47_fb_oclass; +extern struct nvkm_oclass *nv49_fb_oclass; +extern struct nvkm_oclass *nv4e_fb_oclass; +extern struct nvkm_oclass *nv50_fb_oclass; +extern struct nvkm_oclass *g84_fb_oclass; +extern struct nvkm_oclass *gt215_fb_oclass; +extern struct nvkm_oclass *mcp77_fb_oclass; +extern struct nvkm_oclass *mcp89_fb_oclass; +extern struct nvkm_oclass *gf100_fb_oclass; +extern struct nvkm_oclass *gk104_fb_oclass; +extern struct nvkm_oclass *gk20a_fb_oclass; +extern struct nvkm_oclass *gm107_fb_oclass; #include <subdev/bios.h> #include <subdev/bios/ramcfg.h> -struct nouveau_ram_data { +struct nvkm_ram_data { struct list_head head; struct nvbios_ramcfg bios; u32 freq; }; -struct nouveau_ram { - struct nouveau_object base; +struct nvkm_ram { + struct nvkm_object base; enum { NV_MEM_TYPE_UNKNOWN = 0, NV_MEM_TYPE_STOLEN, @@ -140,21 +135,20 @@ struct nouveau_ram { int parts; int part_mask; - int (*get)(struct nouveau_fb *, u64 size, u32 align, - u32 size_nc, u32 type, struct nouveau_mem **); - void (*put)(struct nouveau_fb *, struct nouveau_mem **); + int (*get)(struct nvkm_fb *, u64 size, u32 align, u32 size_nc, + u32 type, struct nvkm_mem **); + void (*put)(struct nvkm_fb *, struct nvkm_mem **); - int (*calc)(struct nouveau_fb *, u32 freq); - int (*prog)(struct nouveau_fb *); - void (*tidy)(struct nouveau_fb *); + int (*calc)(struct nvkm_fb *, u32 freq); + int (*prog)(struct nvkm_fb *); + void (*tidy)(struct nvkm_fb *); u32 freq; u32 mr[16]; u32 mr1_nuts; - struct nouveau_ram_data *next; - struct nouveau_ram_data former; - struct nouveau_ram_data xition; - struct nouveau_ram_data target; + struct nvkm_ram_data *next; + struct nvkm_ram_data former; + struct nvkm_ram_data xition; + struct nvkm_ram_data target; }; - #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index ead3914..393b14c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -100,7 +100,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; @@ -129,7 +129,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; @@ -158,7 +158,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; @@ -187,7 +187,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; @@ -216,7 +216,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; @@ -245,7 +245,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; @@ -274,7 +274,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; @@ -303,7 +303,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; @@ -332,7 +332,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; @@ -361,7 +361,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; @@ -392,7 +392,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; @@ -422,7 +422,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; @@ -452,7 +452,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = g94_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index 56843b0..fc71b67 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -72,7 +72,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -105,7 +105,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -138,7 +138,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -170,7 +170,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -203,7 +203,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -235,7 +235,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -267,7 +267,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -300,7 +300,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -332,7 +332,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index 2abd532..ca6b2a6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -72,7 +72,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -106,7 +106,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -140,7 +140,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -196,7 +196,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -230,7 +230,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -264,7 +264,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; @@ -297,7 +297,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; - device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; + device->oclass[NVDEV_SUBDEV_FB ] = gk104_fb_oclass; device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild index bfd0166..904d601 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild @@ -15,12 +15,12 @@ nvkm-y += nvkm/subdev/fb/nv47.o nvkm-y += nvkm/subdev/fb/nv49.o nvkm-y += nvkm/subdev/fb/nv4e.o nvkm-y += nvkm/subdev/fb/nv50.o -nvkm-y += nvkm/subdev/fb/nv84.o -nvkm-y += nvkm/subdev/fb/nva3.o -nvkm-y += nvkm/subdev/fb/nvaa.o -nvkm-y += nvkm/subdev/fb/nvaf.o -nvkm-y += nvkm/subdev/fb/nvc0.o -nvkm-y += nvkm/subdev/fb/nve0.o +nvkm-y += nvkm/subdev/fb/g84.o +nvkm-y += nvkm/subdev/fb/gt215.o +nvkm-y += nvkm/subdev/fb/mcp77.o +nvkm-y += nvkm/subdev/fb/mcp89.o +nvkm-y += nvkm/subdev/fb/gf100.o +nvkm-y += nvkm/subdev/fb/gk104.o nvkm-y += nvkm/subdev/fb/gk20a.o nvkm-y += nvkm/subdev/fb/gm107.o nvkm-y += nvkm/subdev/fb/ramnv04.o @@ -33,10 +33,10 @@ nvkm-y += nvkm/subdev/fb/ramnv44.o nvkm-y += nvkm/subdev/fb/ramnv49.o nvkm-y += nvkm/subdev/fb/ramnv4e.o nvkm-y += nvkm/subdev/fb/ramnv50.o -nvkm-y += nvkm/subdev/fb/ramnva3.o -nvkm-y += nvkm/subdev/fb/ramnvaa.o -nvkm-y += nvkm/subdev/fb/ramnvc0.o -nvkm-y += nvkm/subdev/fb/ramnve0.o +nvkm-y += nvkm/subdev/fb/ramgt215.o +nvkm-y += nvkm/subdev/fb/rammcp77.o +nvkm-y += nvkm/subdev/fb/ramgf100.o +nvkm-y += nvkm/subdev/fb/ramgk104.o nvkm-y += nvkm/subdev/fb/ramgk20a.o nvkm-y += nvkm/subdev/fb/ramgm107.o nvkm-y += nvkm/subdev/fb/sddr2.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c index 090a7f2..16589fa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c @@ -21,14 +21,13 @@ * * Authors: Ben Skeggs */ +#include "priv.h" #include <subdev/bios.h> #include <subdev/bios/M0203.h> -#include "priv.h" - int -nouveau_fb_bios_memtype(struct nouveau_bios *bios) +nvkm_fb_bios_memtype(struct nvkm_bios *bios) { const u8 ramcfg = (nv_rd32(bios, 0x101000) & 0x0000003c) >> 2; struct nvbios_M0203E M0203E; @@ -51,25 +50,25 @@ nouveau_fb_bios_memtype(struct nouveau_bios *bios) } int -_nouveau_fb_fini(struct nouveau_object *object, bool suspend) +_nvkm_fb_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_fb *pfb = (void *)object; + struct nvkm_fb *pfb = (void *)object; int ret; ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend); if (ret && suspend) return ret; - return nouveau_subdev_fini(&pfb->base, suspend); + return nvkm_subdev_fini(&pfb->base, suspend); } int -_nouveau_fb_init(struct nouveau_object *object) +_nvkm_fb_init(struct nvkm_object *object) { - struct nouveau_fb *pfb = (void *)object; + struct nvkm_fb *pfb = (void *)object; int ret, i; - ret = nouveau_subdev_init(&pfb->base); + ret = nvkm_subdev_init(&pfb->base); if (ret) return ret; @@ -84,25 +83,25 @@ _nouveau_fb_init(struct nouveau_object *object) } void -_nouveau_fb_dtor(struct nouveau_object *object) +_nvkm_fb_dtor(struct nvkm_object *object) { - struct nouveau_fb *pfb = (void *)object; + struct nvkm_fb *pfb = (void *)object; int i; for (i = 0; i < pfb->tile.regions; i++) pfb->tile.fini(pfb, i, &pfb->tile.region[i]); - nouveau_mm_fini(&pfb->tags); - nouveau_mm_fini(&pfb->vram); + nvkm_mm_fini(&pfb->tags); + nvkm_mm_fini(&pfb->vram); - nouveau_object_ref(NULL, (struct nouveau_object **)&pfb->ram); - nouveau_subdev_destroy(&pfb->base); + nvkm_object_ref(NULL, (struct nvkm_object **)&pfb->ram); + nvkm_subdev_destroy(&pfb->base); } int -nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, int length, void **pobject) +nvkm_fb_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { - struct nouveau_fb_impl *impl = (void *)oclass; + struct nvkm_fb_impl *impl = (void *)oclass; static const char *name[] = { [NV_MEM_TYPE_UNKNOWN] = "unknown", [NV_MEM_TYPE_STOLEN ] = "stolen system memory", @@ -116,20 +115,19 @@ nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine, [NV_MEM_TYPE_GDDR4 ] = "GDDR4", [NV_MEM_TYPE_GDDR5 ] = "GDDR5", }; - struct nouveau_object *ram; - struct nouveau_fb *pfb; + struct nvkm_object *ram; + struct nvkm_fb *pfb; int ret; - ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PFB", "fb", - length, pobject); + ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PFB", "fb", + length, pobject); pfb = *pobject; if (ret) return ret; pfb->memtype_valid = impl->memtype; - ret = nouveau_object_ctor(nv_object(pfb), NULL, - impl->ram, NULL, 0, &ram); + ret = nvkm_object_ctor(nv_object(pfb), NULL, impl->ram, NULL, 0, &ram); if (ret) { nv_fatal(pfb, "error detecting memory configuration!!\n"); return ret; @@ -137,15 +135,15 @@ nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine, pfb->ram = (void *)ram; - if (!nouveau_mm_initialised(&pfb->vram)) { - ret = nouveau_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1); + if (!nvkm_mm_initialised(&pfb->vram)) { + ret = nvkm_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1); if (ret) return ret; } - if (!nouveau_mm_initialised(&pfb->tags)) { - ret = nouveau_mm_init(&pfb->tags, 0, pfb->ram->tags ? - ++pfb->ram->tags : 0, 1); + if (!nvkm_mm_initialised(&pfb->tags)) { + ret = nvkm_mm_init(&pfb->tags, 0, pfb->ram->tags ? + ++pfb->ram->tags : 0, 1); if (ret) return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c index cf0e767..6c968d1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.c @@ -21,17 +21,16 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" -struct nouveau_oclass * -nv84_fb_oclass = &(struct nv50_fb_impl) { +struct nvkm_oclass * +g84_fb_oclass = &(struct nv50_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x84), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fb_ctor, .dtor = nv50_fb_dtor, .init = nv50_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, .base.ram = &nv50_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c index d85a25d..15b462a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c @@ -22,8 +22,6 @@ * Authors: Ben Skeggs <bskeggs@redhat.com> * Roy Spliet <rspliet@eclipso.eu> */ - -#include <subdev/bios.h> #include "priv.h" struct ramxlat { @@ -70,7 +68,7 @@ ramgddr3_wr_lo[] = { }; int -nouveau_gddr3_calc(struct nouveau_ram *ram) +nvkm_gddr3_calc(struct nvkm_ram *ram) { int CL, WR, CWL, DLL = 0, ODT = 0, hi; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c index 7fbbe05..f6f9eee 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c @@ -21,8 +21,6 @@ * * Authors: Ben Skeggs <bskeggs@redhat.com> */ - -#include <subdev/bios.h> #include "priv.h" /* binary driver only executes this path if the condition (a) is true @@ -34,7 +32,7 @@ #define NOTE00(a) 1 int -nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts) +nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts) { int pd, lf, xd, vh, vr, vo, l3; int WL, CL, WR, at[2], dt, ds; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c index 32f28dc..5a6c2b7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c @@ -21,22 +21,21 @@ * * Authors: Ben Skeggs */ +#include "gf100.h" -#include "nvc0.h" - -extern const u8 nvc0_pte_storage_type_map[256]; +extern const u8 gf100_pte_storage_type_map[256]; bool -nvc0_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags) +gf100_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags) { u8 memtype = (tile_flags & 0x0000ff00) >> 8; - return likely((nvc0_pte_storage_type_map[memtype] != 0xff)); + return likely((gf100_pte_storage_type_map[memtype] != 0xff)); } static void -nvc0_fb_intr(struct nouveau_subdev *subdev) +gf100_fb_intr(struct nvkm_subdev *subdev) { - struct nvc0_fb_priv *priv = (void *)subdev; + struct gf100_fb_priv *priv = (void *)subdev; u32 intr = nv_rd32(priv, 0x000100); if (intr & 0x08000000) { nv_debug(priv, "PFFB intr\n"); @@ -49,26 +48,27 @@ nvc0_fb_intr(struct nouveau_subdev *subdev) } int -nvc0_fb_init(struct nouveau_object *object) +gf100_fb_init(struct nvkm_object *object) { - struct nvc0_fb_priv *priv = (void *)object; + struct gf100_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; if (priv->r100c10_page) nv_wr32(priv, 0x100c10, priv->r100c10 >> 8); + nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ return 0; } void -nvc0_fb_dtor(struct nouveau_object *object) +gf100_fb_dtor(struct nvkm_object *object) { - struct nouveau_device *device = nv_device(object); - struct nvc0_fb_priv *priv = (void *)object; + struct nvkm_device *device = nv_device(object); + struct gf100_fb_priv *priv = (void *)object; if (priv->r100c10_page) { dma_unmap_page(nv_device_base(device), priv->r100c10, PAGE_SIZE, @@ -76,19 +76,19 @@ nvc0_fb_dtor(struct nouveau_object *object) __free_page(priv->r100c10_page); } - nouveau_fb_destroy(&priv->base); + nvkm_fb_destroy(&priv->base); } int -nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_device *device = nv_device(parent); - struct nvc0_fb_priv *priv; + struct nvkm_device *device = nv_device(parent); + struct gf100_fb_priv *priv; int ret; - ret = nouveau_fb_create(parent, engine, oclass, &priv); + ret = nvkm_fb_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -102,19 +102,19 @@ nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return -EFAULT; } - nv_subdev(priv)->intr = nvc0_fb_intr; + nv_subdev(priv)->intr = gf100_fb_intr; return 0; } -struct nouveau_oclass * -nvc0_fb_oclass = &(struct nouveau_fb_impl) { +struct nvkm_oclass * +gf100_fb_oclass = &(struct nvkm_fb_impl) { .base.handle = NV_SUBDEV(FB, 0xc0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_fb_ctor, - .dtor = nvc0_fb_dtor, - .init = nvc0_fb_init, - .fini = _nouveau_fb_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_fb_ctor, + .dtor = gf100_fb_dtor, + .init = gf100_fb_init, + .fini = _nvkm_fb_fini, }, - .memtype = nvc0_fb_memtype_valid, - .ram = &nvc0_ram_oclass, + .memtype = gf100_fb_memtype_valid, + .ram = &gf100_ram_oclass, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h new file mode 100644 index 0000000..0af4da2 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.h @@ -0,0 +1,28 @@ +#ifndef __NVKM_RAM_NVC0_H__ +#define __NVKM_RAM_NVC0_H__ +#include "priv.h" +#include "nv50.h" + +struct gf100_fb_priv { + struct nvkm_fb base; + struct page *r100c10_page; + dma_addr_t r100c10; +}; + +int gf100_fb_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void gf100_fb_dtor(struct nvkm_object *); +int gf100_fb_init(struct nvkm_object *); +bool gf100_fb_memtype_valid(struct nvkm_fb *, u32); + +#define gf100_ram_create(p,e,o,m,d) \ + gf100_ram_create_((p), (e), (o), (m), sizeof(**d), (void **)d) +int gf100_ram_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, u32, int, void **); +int gf100_ram_get(struct nvkm_fb *, u64, u32, u32, u32, + struct nvkm_mem **); +void gf100_ram_put(struct nvkm_fb *, struct nvkm_mem **); + +int gk104_ram_init(struct nvkm_object*); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c index 595db50..1c08317 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.c @@ -21,18 +21,17 @@ * * Authors: Ben Skeggs */ +#include "gf100.h" -#include "nvc0.h" - -struct nouveau_oclass * -nve0_fb_oclass = &(struct nouveau_fb_impl) { +struct nvkm_oclass * +gk104_fb_oclass = &(struct nvkm_fb_impl) { .base.handle = NV_SUBDEV(FB, 0xe0), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_fb_ctor, - .dtor = nvc0_fb_dtor, - .init = nvc0_fb_init, - .fini = _nouveau_fb_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_fb_ctor, + .dtor = gf100_fb_dtor, + .init = gf100_fb_init, + .fini = _nvkm_fb_fini, }, - .memtype = nvc0_fb_memtype_valid, - .ram = &nve0_ram_oclass, + .memtype = gf100_fb_memtype_valid, + .ram = &gk104_ram_oclass, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c index fde42e4..6762847 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c @@ -19,20 +19,19 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - -#include "nvc0.h" +#include "gf100.h" struct gk20a_fb_priv { - struct nouveau_fb base; + struct nvkm_fb base; }; static int -gk20a_fb_init(struct nouveau_object *object) +gk20a_fb_init(struct nvkm_object *object) { struct gk20a_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -41,14 +40,14 @@ gk20a_fb_init(struct nouveau_object *object) } static int -gk20a_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk20a_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct gk20a_fb_priv *priv; int ret; - ret = nouveau_fb_create(parent, engine, oclass, &priv); + ret = nvkm_fb_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -56,15 +55,15 @@ gk20a_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * -gk20a_fb_oclass = &(struct nouveau_fb_impl) { +struct nvkm_oclass * +gk20a_fb_oclass = &(struct nvkm_fb_impl) { .base.handle = NV_SUBDEV(FB, 0xea), - .base.ofuncs = &(struct nouveau_ofuncs) { + .base.ofuncs = &(struct nvkm_ofuncs) { .ctor = gk20a_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = gk20a_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, - .memtype = nvc0_fb_memtype_valid, + .memtype = gf100_fb_memtype_valid, .ram = &gk20a_ram_oclass, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c index c4840ae..843f935 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.c @@ -21,18 +21,17 @@ * * Authors: Ben Skeggs */ +#include "gf100.h" -#include "nvc0.h" - -struct nouveau_oclass * -gm107_fb_oclass = &(struct nouveau_fb_impl) { +struct nvkm_oclass * +gm107_fb_oclass = &(struct nvkm_fb_impl) { .base.handle = NV_SUBDEV(FB, 0x07), - .base.ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_fb_ctor, - .dtor = nvc0_fb_dtor, - .init = nvc0_fb_init, - .fini = _nouveau_fb_fini, + .base.ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_fb_ctor, + .dtor = gf100_fb_dtor, + .init = gf100_fb_init, + .fini = _nvkm_fb_fini, }, - .memtype = nvc0_fb_memtype_valid, + .memtype = gf100_fb_memtype_valid, .ram = &gm107_ram_oclass, }.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c index dab6e1c..dd9b8a0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.c @@ -21,19 +21,18 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" -struct nouveau_oclass * -nva3_fb_oclass = &(struct nv50_fb_impl) { +struct nvkm_oclass * +gt215_fb_oclass = &(struct nv50_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0xa3), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fb_ctor, .dtor = nv50_fb_dtor, .init = nv50_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, - .base.ram = &nva3_ram_oclass, + .base.ram = >215_ram_oclass, .trap = 0x000d0fff, }.base.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c index cba8e68..7be4a47 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaa.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.c @@ -21,19 +21,18 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" -struct nouveau_oclass * -nvaa_fb_oclass = &(struct nv50_fb_impl) { +struct nvkm_oclass * +mcp77_fb_oclass = &(struct nv50_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0xaa), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fb_ctor, .dtor = nv50_fb_dtor, .init = nv50_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, - .base.ram = &nvaa_ram_oclass, + .base.ram = &mcp77_ram_oclass, .trap = 0x001d07ff, }.base.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c index 5423faa..2d00656 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvaf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.c @@ -21,19 +21,18 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" -struct nouveau_oclass * -nvaf_fb_oclass = &(struct nv50_fb_impl) { +struct nvkm_oclass * +mcp89_fb_oclass = &(struct nv50_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0xaf), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fb_ctor, .dtor = nv50_fb_dtor, .init = nv50_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, - .base.ram = &nvaa_ram_oclass, + .base.ram = &mcp77_ram_oclass, .trap = 0x089d1fff, }.base.base; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c index 8309fe3..c063dec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c @@ -21,13 +21,11 @@ * * Authors: Ben Skeggs */ - #include "nv04.h" - -#define NV04_PFB_CFG0 0x00100200 +#include "regsnv04.h" bool -nv04_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags) +nv04_fb_memtype_valid(struct nvkm_fb *pfb, u32 tile_flags) { if (!(tile_flags & 0xff00)) return true; @@ -36,12 +34,12 @@ nv04_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags) } static int -nv04_fb_init(struct nouveau_object *object) +nv04_fb_init(struct nvkm_object *object) { struct nv04_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -54,15 +52,15 @@ nv04_fb_init(struct nouveau_object *object) } int -nv04_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_fb_impl *impl = (void *)oclass; struct nv04_fb_priv *priv; int ret; - ret = nouveau_fb_create(parent, engine, oclass, &priv); + ret = nvkm_fb_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -75,14 +73,14 @@ nv04_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv04_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x04), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv04_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv04_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h index 06ce71f..caa0d03 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.h @@ -1,55 +1,53 @@ #ifndef __NVKM_FB_NV04_H__ #define __NVKM_FB_NV04_H__ - #include "priv.h" struct nv04_fb_priv { - struct nouveau_fb base; + struct nvkm_fb base; }; -int nv04_fb_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); +int nv04_fb_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); struct nv04_fb_impl { - struct nouveau_fb_impl base; + struct nvkm_fb_impl base; struct { int regions; - void (*init)(struct nouveau_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nouveau_fb_tile *); - void (*comp)(struct nouveau_fb *, int i, u32 size, u32 flags, - struct nouveau_fb_tile *); - void (*fini)(struct nouveau_fb *, int i, - struct nouveau_fb_tile *); - void (*prog)(struct nouveau_fb *, int i, - struct nouveau_fb_tile *); + void (*init)(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); + void (*comp)(struct nvkm_fb *, int i, u32 size, u32 flags, + struct nvkm_fb_tile *); + void (*fini)(struct nvkm_fb *, int i, + struct nvkm_fb_tile *); + void (*prog)(struct nvkm_fb *, int i, + struct nvkm_fb_tile *); } tile; }; -void nv10_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nouveau_fb_tile *); -void nv10_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *); -void nv10_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); - -void nv20_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nouveau_fb_tile *); -void nv20_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *); -void nv20_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); +void nv10_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); +void nv10_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *); +void nv10_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); -int nv30_fb_init(struct nouveau_object *); -void nv30_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nouveau_fb_tile *); +void nv20_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); +void nv20_fb_tile_fini(struct nvkm_fb *, int i, struct nvkm_fb_tile *); +void nv20_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); -void nv40_fb_tile_comp(struct nouveau_fb *, int i, u32 size, u32 flags, - struct nouveau_fb_tile *); +int nv30_fb_init(struct nvkm_object *); +void nv30_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); -int nv41_fb_init(struct nouveau_object *); -void nv41_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); +void nv40_fb_tile_comp(struct nvkm_fb *, int i, u32 size, u32 flags, + struct nvkm_fb_tile *); -int nv44_fb_init(struct nouveau_object *); -void nv44_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); +int nv41_fb_init(struct nvkm_object *); +void nv41_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); -void nv46_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, - u32 pitch, u32 flags, struct nouveau_fb_tile *); +int nv44_fb_init(struct nvkm_object *); +void nv44_fb_tile_prog(struct nvkm_fb *, int, struct nvkm_fb_tile *); +void nv46_fb_tile_init(struct nvkm_fb *, int i, u32 addr, u32 size, + u32 pitch, u32 flags, struct nvkm_fb_tile *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c index ffb7ec6..f3530e4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c @@ -23,12 +23,11 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" void -nv10_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, - u32 flags, struct nouveau_fb_tile *tile) +nv10_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, + u32 flags, struct nvkm_fb_tile *tile) { tile->addr = 0x80000000 | addr; tile->limit = max(1u, addr + size) - 1; @@ -36,7 +35,7 @@ nv10_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, } void -nv10_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +nv10_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) { tile->addr = 0; tile->limit = 0; @@ -45,7 +44,7 @@ nv10_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) } void -nv10_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +nv10_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) { nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); @@ -53,14 +52,14 @@ nv10_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) nv_rd32(pfb, 0x100240 + (i * 0x10)); } -struct nouveau_oclass * +struct nvkm_oclass * nv10_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x10), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, - .init = _nouveau_fb_init, - .fini = _nouveau_fb_fini, + .dtor = _nvkm_fb_dtor, + .init = _nvkm_fb_init, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv10_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c index 265d125..83bcb73 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.c @@ -23,17 +23,16 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" -struct nouveau_oclass * +struct nvkm_oclass * nv1a_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x1a), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, - .init = _nouveau_fb_init, - .fini = _nouveau_fb_fini, + .dtor = _nvkm_fb_dtor, + .init = _nvkm_fb_init, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv1a_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c index 2209ade..e37084b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c @@ -23,12 +23,11 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" void -nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, - u32 flags, struct nouveau_fb_tile *tile) +nv20_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, + u32 flags, struct nvkm_fb_tile *tile) { tile->addr = 0x00000001 | addr; tile->limit = max(1u, addr + size) - 1; @@ -40,12 +39,12 @@ nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, } static void -nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, - struct nouveau_fb_tile *tile) +nv20_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, + struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ else tile->zcomp = 0x04000000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; @@ -57,17 +56,17 @@ nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, } void -nv20_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +nv20_fb_tile_fini(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) { tile->addr = 0; tile->limit = 0; tile->pitch = 0; tile->zcomp = 0; - nouveau_mm_free(&pfb->tags, &tile->tag); + nvkm_mm_free(&pfb->tags, &tile->tag); } void -nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +nv20_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) { nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); @@ -76,14 +75,14 @@ nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) nv_wr32(pfb, 0x100300 + (i * 0x04), tile->zcomp); } -struct nouveau_oclass * +struct nvkm_oclass * nv20_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x20), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, - .init = _nouveau_fb_init, - .fini = _nouveau_fb_fini, + .dtor = _nvkm_fb_dtor, + .init = _nvkm_fb_init, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv20_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c index e2a66c3..bc9f54f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.c @@ -23,16 +23,15 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" static void -nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, - struct nouveau_fb_tile *tile) +nv25_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, + struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ else tile->zcomp = 0x00200000; /* Z24S8 */ tile->zcomp |= tile->tag->offset; @@ -42,14 +41,14 @@ nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, } } -struct nouveau_oclass * +struct nvkm_oclass * nv25_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x25), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, - .init = _nouveau_fb_init, - .fini = _nouveau_fb_fini, + .dtor = _nvkm_fb_dtor, + .init = _nvkm_fb_init, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv20_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c index cbec402..6c0b82f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c @@ -23,12 +23,11 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" void -nv30_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, - u32 flags, struct nouveau_fb_tile *tile) +nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, + u32 flags, struct nvkm_fb_tile *tile) { /* for performance, select alternate bank offset for zeta */ if (!(flags & 4)) { @@ -46,12 +45,12 @@ nv30_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, } static void -nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, - struct nouveau_fb_tile *tile) +nv30_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, + struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */ else tile->zcomp |= 0x02000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -65,7 +64,7 @@ nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, static int calc_bias(struct nv04_fb_priv *priv, int k, int i, int j) { - struct nouveau_device *device = nv_device(priv); + struct nvkm_device *device = nv_device(priv); int b = (device->chipset > 0x30 ? nv_rd32(priv, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) : 0) & 0xf; @@ -88,13 +87,13 @@ calc_ref(struct nv04_fb_priv *priv, int l, int k, int i) } int -nv30_fb_init(struct nouveau_object *object) +nv30_fb_init(struct nvkm_object *object) { - struct nouveau_device *device = nv_device(object); + struct nvkm_device *device = nv_device(object); struct nv04_fb_priv *priv = (void *)object; int ret, i, j; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -120,14 +119,14 @@ nv30_fb_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv30_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x30), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv30_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv20_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c index b2cf8c6..c01dc18 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.c @@ -23,16 +23,15 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" static void -nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, - struct nouveau_fb_tile *tile) +nv35_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, + struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ else tile->zcomp |= 0x08000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -43,14 +42,14 @@ nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, } } -struct nouveau_oclass * +struct nvkm_oclass * nv35_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x35), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv30_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv20_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c index b4cdae2a..cad75a1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.c @@ -23,16 +23,15 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" static void -nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, - struct nouveau_fb_tile *tile) +nv36_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, + struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x40); u32 tags = round_up(tiles / pfb->ram->parts, 0x40); - if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + if (!nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ else tile->zcomp |= 0x20000000; /* Z24S8 */ tile->zcomp |= ((tile->tag->offset ) >> 6); @@ -43,14 +42,14 @@ nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, } } -struct nouveau_oclass * +struct nvkm_oclass * nv36_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x36), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv30_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv20_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c index 5281425..dbe5c19 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c @@ -23,17 +23,16 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" void -nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, - struct nouveau_fb_tile *tile) +nv40_fb_tile_comp(struct nvkm_fb *pfb, int i, u32 size, u32 flags, + struct nvkm_fb_tile *tile) { u32 tiles = DIV_ROUND_UP(size, 0x80); u32 tags = round_up(tiles / pfb->ram->parts, 0x100); if ( (flags & 2) && - !nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { + !nvkm_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ tile->zcomp |= ((tile->tag->offset ) >> 8); tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; @@ -44,12 +43,12 @@ nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, } static int -nv40_fb_init(struct nouveau_object *object) +nv40_fb_init(struct nvkm_object *object) { struct nv04_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -57,14 +56,14 @@ nv40_fb_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv40_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x40), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv40_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv40_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h index 581f808..6021826 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.h @@ -1,17 +1,14 @@ #ifndef __NVKM_FB_NV40_H__ #define __NVKM_FB_NV40_H__ - #include "priv.h" struct nv40_ram { - struct nouveau_ram base; + struct nvkm_ram base; u32 ctrl; u32 coef; }; - -int nv40_ram_calc(struct nouveau_fb *, u32); -int nv40_ram_prog(struct nouveau_fb *); -void nv40_ram_tidy(struct nouveau_fb *); - +int nv40_ram_calc(struct nvkm_fb *, u32); +int nv40_ram_prog(struct nvkm_fb *); +void nv40_ram_tidy(struct nvkm_fb *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c index b239a86..d9e1a40 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c @@ -23,11 +23,10 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" void -nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +nv41_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) { nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); @@ -37,12 +36,12 @@ nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) } int -nv41_fb_init(struct nouveau_object *object) +nv41_fb_init(struct nvkm_object *object) { struct nv04_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -50,14 +49,14 @@ nv41_fb_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv41_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x41), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv41_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv41_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c index d847820..20b97c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c @@ -23,12 +23,11 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" static void -nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, - u32 flags, struct nouveau_fb_tile *tile) +nv44_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, + u32 flags, struct nvkm_fb_tile *tile) { tile->addr = 0x00000001; /* mode = vram */ tile->addr |= addr; @@ -37,7 +36,7 @@ nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, } void -nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +nv44_fb_tile_prog(struct nvkm_fb *pfb, int i, struct nvkm_fb_tile *tile) { nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); @@ -46,12 +45,12 @@ nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) } int -nv44_fb_init(struct nouveau_object *object) +nv44_fb_init(struct nvkm_object *object) { struct nv04_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -60,14 +59,14 @@ nv44_fb_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv44_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x44), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv44_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv44_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c index a5b7751..5bfac38 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.c @@ -23,12 +23,11 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" void -nv46_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, - u32 flags, struct nouveau_fb_tile *tile) +nv46_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, + u32 flags, struct nvkm_fb_tile *tile) { /* for performance, select alternate bank offset for zeta */ if (!(flags & 4)) tile->addr = (0 << 3); @@ -40,14 +39,14 @@ nv46_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, tile->pitch = pitch; } -struct nouveau_oclass * +struct nvkm_oclass * nv46_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x46), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv44_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv44_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c index 3bea142..d3b3988 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.c @@ -23,17 +23,16 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" -struct nouveau_oclass * +struct nvkm_oclass * nv47_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x47), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv41_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv41_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c index 666cbd5..236e36c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.c @@ -23,17 +23,16 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" -struct nouveau_oclass * +struct nvkm_oclass * nv49_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x49), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv41_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv49_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c index 42e64f3..1352b6a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.c @@ -23,17 +23,16 @@ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. * */ - #include "nv04.h" -struct nouveau_oclass * +struct nvkm_oclass * nv4e_fb_oclass = &(struct nv04_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x4e), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_fb_ctor, - .dtor = _nouveau_fb_dtor, + .dtor = _nvkm_fb_dtor, .init = nv44_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv04_fb_memtype_valid, .base.ram = &nv4e_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 962273e..48fd5a5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -21,15 +21,11 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" #include <core/client.h> -#include <core/enum.h> #include <core/engctx.h> -#include <core/object.h> - -#include <subdev/bios.h> - -#include "nv50.h" +#include <core/enum.h> int nv50_fb_memtype[0x80] = { @@ -44,12 +40,12 @@ nv50_fb_memtype[0x80] = { }; bool -nv50_fb_memtype_valid(struct nouveau_fb *pfb, u32 memtype) +nv50_fb_memtype_valid(struct nvkm_fb *pfb, u32 memtype) { return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0; } -static const struct nouveau_enum vm_dispatch_subclients[] = { +static const struct nvkm_enum vm_dispatch_subclients[] = { { 0x00000000, "GRCTX", NULL }, { 0x00000001, "NOTIFY", NULL }, { 0x00000002, "QUERY", NULL }, @@ -60,14 +56,14 @@ static const struct nouveau_enum vm_dispatch_subclients[] = { {} }; -static const struct nouveau_enum vm_ccache_subclients[] = { +static const struct nvkm_enum vm_ccache_subclients[] = { { 0x00000000, "CB", NULL }, { 0x00000001, "TIC", NULL }, { 0x00000002, "TSC", NULL }, {} }; -static const struct nouveau_enum vm_prop_subclients[] = { +static const struct nvkm_enum vm_prop_subclients[] = { { 0x00000000, "RT0", NULL }, { 0x00000001, "RT1", NULL }, { 0x00000002, "RT2", NULL }, @@ -84,19 +80,19 @@ static const struct nouveau_enum vm_prop_subclients[] = { {} }; -static const struct nouveau_enum vm_pfifo_subclients[] = { +static const struct nvkm_enum vm_pfifo_subclients[] = { { 0x00000000, "PUSHBUF", NULL }, { 0x00000001, "SEMAPHORE", NULL }, {} }; -static const struct nouveau_enum vm_bar_subclients[] = { +static const struct nvkm_enum vm_bar_subclients[] = { { 0x00000000, "FB", NULL }, { 0x00000001, "IN", NULL }, {} }; -static const struct nouveau_enum vm_client[] = { +static const struct nvkm_enum vm_client[] = { { 0x00000000, "STRMOUT", NULL }, { 0x00000003, "DISPATCH", vm_dispatch_subclients }, { 0x00000004, "PFIFO_WRITE", NULL }, @@ -115,7 +111,7 @@ static const struct nouveau_enum vm_client[] = { {} }; -static const struct nouveau_enum vm_engine[] = { +static const struct nvkm_enum vm_engine[] = { { 0x00000000, "PGRAPH", NULL, NVDEV_ENGINE_GR }, { 0x00000001, "PVP", NULL, NVDEV_ENGINE_VP }, { 0x00000004, "PEEPHOLE", NULL }, @@ -132,7 +128,7 @@ static const struct nouveau_enum vm_engine[] = { {} }; -static const struct nouveau_enum vm_fault[] = { +static const struct nvkm_enum vm_fault[] = { { 0x00000000, "PT_NOT_PRESENT", NULL }, { 0x00000001, "PT_TOO_SHORT", NULL }, { 0x00000002, "PAGE_NOT_PRESENT", NULL }, @@ -146,13 +142,13 @@ static const struct nouveau_enum vm_fault[] = { }; static void -nv50_fb_intr(struct nouveau_subdev *subdev) +nv50_fb_intr(struct nvkm_subdev *subdev) { - struct nouveau_device *device = nv_device(subdev); - struct nouveau_engine *engine; + struct nvkm_device *device = nv_device(subdev); + struct nvkm_engine *engine; struct nv50_fb_priv *priv = (void *)subdev; - const struct nouveau_enum *en, *cl; - struct nouveau_object *engctx = NULL; + const struct nvkm_enum *en, *cl; + struct nvkm_object *engctx = NULL; u32 trap[6], idx, chan; u8 st0, st1, st2, st3; int i; @@ -183,21 +179,21 @@ nv50_fb_intr(struct nouveau_subdev *subdev) } chan = (trap[2] << 16) | trap[1]; - en = nouveau_enum_find(vm_engine, st0); + en = nvkm_enum_find(vm_engine, st0); if (en && en->data2) { - const struct nouveau_enum *orig_en = en; + const struct nvkm_enum *orig_en = en; while (en->name && en->value == st0 && en->data2) { - engine = nouveau_engine(subdev, en->data2); + engine = nvkm_engine(subdev, en->data2); /*XXX: clean this up */ if (!engine && en->data2 == NVDEV_ENGINE_BSP) - engine = nouveau_engine(subdev, NVDEV_ENGINE_MSVLD); + engine = nvkm_engine(subdev, NVDEV_ENGINE_MSVLD); if (!engine && en->data2 == NVDEV_ENGINE_CIPHER) - engine = nouveau_engine(subdev, NVDEV_ENGINE_SEC); + engine = nvkm_engine(subdev, NVDEV_ENGINE_SEC); if (!engine && en->data2 == NVDEV_ENGINE_VP) - engine = nouveau_engine(subdev, NVDEV_ENGINE_MSPDEC); + engine = nvkm_engine(subdev, NVDEV_ENGINE_MSPDEC); if (engine) { - engctx = nouveau_engctx_get(engine, chan); + engctx = nvkm_engctx_get(engine, chan); if (engctx) break; } @@ -210,23 +206,23 @@ nv50_fb_intr(struct nouveau_subdev *subdev) nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ", (trap[5] & 0x00000100) ? "read" : "write", trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan, - nouveau_client_name(engctx)); + nvkm_client_name(engctx)); - nouveau_engctx_put(engctx); + nvkm_engctx_put(engctx); if (en) pr_cont("%s/", en->name); else pr_cont("%02x/", st0); - cl = nouveau_enum_find(vm_client, st2); + cl = nvkm_enum_find(vm_client, st2); if (cl) pr_cont("%s/", cl->name); else pr_cont("%02x/", st2); - if (cl && cl->data) cl = nouveau_enum_find(cl->data, st3); - else if (en && en->data) cl = nouveau_enum_find(en->data, st3); + if (cl && cl->data) cl = nvkm_enum_find(cl->data, st3); + else if (en && en->data) cl = nvkm_enum_find(en->data, st3); else cl = NULL; if (cl) pr_cont("%s", cl->name); @@ -234,7 +230,7 @@ nv50_fb_intr(struct nouveau_subdev *subdev) pr_cont("%02x", st3); pr_cont(" reason: "); - en = nouveau_enum_find(vm_fault, st1); + en = nvkm_enum_find(vm_fault, st1); if (en) pr_cont("%s\n", en->name); else @@ -242,15 +238,15 @@ nv50_fb_intr(struct nouveau_subdev *subdev) } int -nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_device *device = nv_device(parent); + struct nvkm_device *device = nv_device(parent); struct nv50_fb_priv *priv; int ret; - ret = nouveau_fb_create(parent, engine, oclass, &priv); + ret = nvkm_fb_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -271,9 +267,9 @@ nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } void -nv50_fb_dtor(struct nouveau_object *object) +nv50_fb_dtor(struct nvkm_object *object) { - struct nouveau_device *device = nv_device(object); + struct nvkm_device *device = nv_device(object); struct nv50_fb_priv *priv = (void *)object; if (priv->r100c08_page) { @@ -282,17 +278,17 @@ nv50_fb_dtor(struct nouveau_object *object) __free_page(priv->r100c08_page); } - nouveau_fb_destroy(&priv->base); + nvkm_fb_destroy(&priv->base); } int -nv50_fb_init(struct nouveau_object *object) +nv50_fb_init(struct nvkm_object *object) { struct nv50_fb_impl *impl = (void *)object->oclass; struct nv50_fb_priv *priv = (void *)object; int ret; - ret = nouveau_fb_init(&priv->base); + ret = nvkm_fb_init(&priv->base); if (ret) return ret; @@ -308,14 +304,14 @@ nv50_fb_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass * +struct nvkm_oclass * nv50_fb_oclass = &(struct nv50_fb_impl) { .base.base.handle = NV_SUBDEV(FB, 0x50), - .base.base.ofuncs = &(struct nouveau_ofuncs) { + .base.base.ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_fb_ctor, .dtor = nv50_fb_dtor, .init = nv50_fb_init, - .fini = _nouveau_fb_fini, + .fini = _nvkm_fb_fini, }, .base.memtype = nv50_fb_memtype_valid, .base.ram = &nv50_ram_oclass, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h index c5e5a88..f3cde3f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.h @@ -1,33 +1,31 @@ #ifndef __NVKM_FB_NV50_H__ #define __NVKM_FB_NV50_H__ - #include "priv.h" struct nv50_fb_priv { - struct nouveau_fb base; + struct nvkm_fb base; struct page *r100c08_page; dma_addr_t r100c08; }; -int nv50_fb_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nv50_fb_dtor(struct nouveau_object *); -int nv50_fb_init(struct nouveau_object *); +int nv50_fb_ctor(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, void *, u32, + struct nvkm_object **); +void nv50_fb_dtor(struct nvkm_object *); +int nv50_fb_init(struct nvkm_object *); struct nv50_fb_impl { - struct nouveau_fb_impl base; + struct nvkm_fb_impl base; u32 trap; }; #define nv50_ram_create(p,e,o,d) \ nv50_ram_create_((p), (e), (o), sizeof(**d), (void **)d) -int nv50_ram_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -int nv50_ram_get(struct nouveau_fb *, u64 size, u32 align, u32 ncmin, - u32 memtype, struct nouveau_mem **); -void nv50_ram_put(struct nouveau_fb *, struct nouveau_mem **); -void __nv50_ram_put(struct nouveau_fb *, struct nouveau_mem *); +int nv50_ram_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +int nv50_ram_get(struct nvkm_fb *, u64 size, u32 align, u32 ncmin, + u32 memtype, struct nvkm_mem **); +void nv50_ram_put(struct nvkm_fb *, struct nvkm_mem **); +void __nv50_ram_put(struct nvkm_fb *, struct nvkm_mem *); extern int nv50_fb_memtype[0x80]; - #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.h deleted file mode 100644 index 705a06d..0000000 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nvc0.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef __NVKM_RAM_NVC0_H__ -#define __NVKM_RAM_NVC0_H__ - -#include "priv.h" -#include "nv50.h" - -struct nvc0_fb_priv { - struct nouveau_fb base; - struct page *r100c10_page; - dma_addr_t r100c10; -}; - -int nvc0_fb_ctor(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, void *, u32, - struct nouveau_object **); -void nvc0_fb_dtor(struct nouveau_object *); -int nvc0_fb_init(struct nouveau_object *); -bool nvc0_fb_memtype_valid(struct nouveau_fb *, u32); - - -#define nvc0_ram_create(p,e,o,m,d) \ - nvc0_ram_create_((p), (e), (o), (m), sizeof(**d), (void **)d) -int nvc0_ram_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, u32, int, void **); -int nvc0_ram_get(struct nouveau_fb *, u64, u32, u32, u32, - struct nouveau_mem **); -void nvc0_ram_put(struct nouveau_fb *, struct nouveau_mem **); - -int nve0_ram_init(struct nouveau_object*); - -#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h index 283863f..d82da02 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/priv.h @@ -1,76 +1,74 @@ #ifndef __NVKM_FB_PRIV_H__ #define __NVKM_FB_PRIV_H__ - #include <subdev/fb.h> +struct nvkm_bios; -#define nouveau_ram_create(p,e,o,d) \ - nouveau_object_create_((p), (e), (o), 0, sizeof(**d), (void **)d) -#define nouveau_ram_destroy(p) \ - nouveau_object_destroy(&(p)->base) -#define nouveau_ram_init(p) \ - nouveau_object_init(&(p)->base) -#define nouveau_ram_fini(p,s) \ - nouveau_object_fini(&(p)->base, (s)) +#define nvkm_ram_create(p,e,o,d) \ + nvkm_object_create_((p), (e), (o), 0, sizeof(**d), (void **)d) +#define nvkm_ram_destroy(p) \ + nvkm_object_destroy(&(p)->base) +#define nvkm_ram_init(p) \ + nvkm_object_init(&(p)->base) +#define nvkm_ram_fini(p,s) \ + nvkm_object_fini(&(p)->base, (s)) -#define nouveau_ram_create_(p,e,o,s,d) \ - nouveau_object_create_((p), (e), (o), 0, (s), (void **)d) -#define _nouveau_ram_dtor nouveau_object_destroy -#define _nouveau_ram_init nouveau_object_init -#define _nouveau_ram_fini nouveau_object_fini +#define nvkm_ram_create_(p,e,o,s,d) \ + nvkm_object_create_((p), (e), (o), 0, (s), (void **)d) +#define _nvkm_ram_dtor nvkm_object_destroy +#define _nvkm_ram_init nvkm_object_init +#define _nvkm_ram_fini nvkm_object_fini -extern struct nouveau_oclass nv04_ram_oclass; -extern struct nouveau_oclass nv10_ram_oclass; -extern struct nouveau_oclass nv1a_ram_oclass; -extern struct nouveau_oclass nv20_ram_oclass; -extern struct nouveau_oclass nv40_ram_oclass; -extern struct nouveau_oclass nv41_ram_oclass; -extern struct nouveau_oclass nv44_ram_oclass; -extern struct nouveau_oclass nv49_ram_oclass; -extern struct nouveau_oclass nv4e_ram_oclass; -extern struct nouveau_oclass nv50_ram_oclass; -extern struct nouveau_oclass nva3_ram_oclass; -extern struct nouveau_oclass nvaa_ram_oclass; -extern struct nouveau_oclass nvc0_ram_oclass; -extern struct nouveau_oclass nve0_ram_oclass; -extern struct nouveau_oclass gk20a_ram_oclass; -extern struct nouveau_oclass gm107_ram_oclass; +extern struct nvkm_oclass nv04_ram_oclass; +extern struct nvkm_oclass nv10_ram_oclass; +extern struct nvkm_oclass nv1a_ram_oclass; +extern struct nvkm_oclass nv20_ram_oclass; +extern struct nvkm_oclass nv40_ram_oclass; +extern struct nvkm_oclass nv41_ram_oclass; +extern struct nvkm_oclass nv44_ram_oclass; +extern struct nvkm_oclass nv49_ram_oclass; +extern struct nvkm_oclass nv4e_ram_oclass; +extern struct nvkm_oclass nv50_ram_oclass; +extern struct nvkm_oclass gt215_ram_oclass; +extern struct nvkm_oclass mcp77_ram_oclass; +extern struct nvkm_oclass gf100_ram_oclass; +extern struct nvkm_oclass gk104_ram_oclass; +extern struct nvkm_oclass gk20a_ram_oclass; +extern struct nvkm_oclass gm107_ram_oclass; -int nouveau_sddr2_calc(struct nouveau_ram *ram); -int nouveau_sddr3_calc(struct nouveau_ram *ram); -int nouveau_gddr3_calc(struct nouveau_ram *ram); -int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts); +int nvkm_sddr2_calc(struct nvkm_ram *ram); +int nvkm_sddr3_calc(struct nvkm_ram *ram); +int nvkm_gddr3_calc(struct nvkm_ram *ram); +int nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts); -#define nouveau_fb_create(p,e,c,d) \ - nouveau_fb_create_((p), (e), (c), sizeof(**d), (void **)d) -#define nouveau_fb_destroy(p) ({ \ - struct nouveau_fb *pfb = (p); \ - _nouveau_fb_dtor(nv_object(pfb)); \ +#define nvkm_fb_create(p,e,c,d) \ + nvkm_fb_create_((p), (e), (c), sizeof(**d), (void **)d) +#define nvkm_fb_destroy(p) ({ \ + struct nvkm_fb *pfb = (p); \ + _nvkm_fb_dtor(nv_object(pfb)); \ }) -#define nouveau_fb_init(p) ({ \ - struct nouveau_fb *pfb = (p); \ - _nouveau_fb_init(nv_object(pfb)); \ +#define nvkm_fb_init(p) ({ \ + struct nvkm_fb *pfb = (p); \ + _nvkm_fb_init(nv_object(pfb)); \ }) -#define nouveau_fb_fini(p,s) ({ \ - struct nouveau_fb *pfb = (p); \ - _nouveau_fb_fini(nv_object(pfb), (s)); \ +#define nvkm_fb_fini(p,s) ({ \ + struct nvkm_fb *pfb = (p); \ + _nvkm_fb_fini(nv_object(pfb), (s)); \ }) -int nouveau_fb_create_(struct nouveau_object *, struct nouveau_object *, - struct nouveau_oclass *, int, void **); -void _nouveau_fb_dtor(struct nouveau_object *); -int _nouveau_fb_init(struct nouveau_object *); -int _nouveau_fb_fini(struct nouveau_object *, bool); +int nvkm_fb_create_(struct nvkm_object *, struct nvkm_object *, + struct nvkm_oclass *, int, void **); +void _nvkm_fb_dtor(struct nvkm_object *); +int _nvkm_fb_init(struct nvkm_object *); +int _nvkm_fb_fini(struct nvkm_object *, bool); -struct nouveau_fb_impl { - struct nouveau_oclass base; - struct nouveau_oclass *ram; - bool (*memtype)(struct nouveau_fb *, u32); +struct nvkm_fb_impl { + struct nvkm_oclass base; + struct nvkm_oclass *ram; + bool (*memtype)(struct nvkm_fb *, u32); }; -bool nv04_fb_memtype_valid(struct nouveau_fb *, u32 memtype); -bool nv50_fb_memtype_valid(struct nouveau_fb *, u32 memtype); - -struct nouveau_bios; -int nouveau_fb_bios_memtype(struct nouveau_bios *); +bool nv04_fb_memtype_valid(struct nvkm_fb *, u32 memtype); +bool nv50_fb_memtype_valid(struct nvkm_fb *, u32 memtype); +int nvkm_fb_bios_memtype(struct nvkm_bios *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h index f641f3a..f343682 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h @@ -1,11 +1,10 @@ #ifndef __NVKM_FBRAM_FUC_H__ #define __NVKM_FBRAM_FUC_H__ - #include <subdev/pmu.h> struct ramfuc { - struct nouveau_memx *memx; - struct nouveau_fb *pfb; + struct nvkm_memx *memx; + struct nvkm_fb *pfb; int sequence; }; @@ -55,12 +54,12 @@ ramfuc_reg(u32 addr) } static inline int -ramfuc_init(struct ramfuc *ram, struct nouveau_fb *pfb) +ramfuc_init(struct ramfuc *ram, struct nvkm_fb *pfb) { - struct nouveau_pmu *pmu = nouveau_pmu(pfb); + struct nvkm_pmu *pmu = nvkm_pmu(pfb); int ret; - ret = nouveau_memx_init(pmu, &ram->memx); + ret = nvkm_memx_init(pmu, &ram->memx); if (ret) return ret; @@ -74,7 +73,7 @@ ramfuc_exec(struct ramfuc *ram, bool exec) { int ret = 0; if (ram->pfb) { - ret = nouveau_memx_fini(&ram->memx, exec); + ret = nvkm_memx_fini(&ram->memx, exec); ram->pfb = NULL; } return ret; @@ -97,10 +96,8 @@ ramfuc_wr32(struct ramfuc *ram, struct ramfuc_reg *reg, u32 data) reg->data = data; for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { - if (mask & 1) { - nouveau_memx_wr32(ram->memx, reg->addr+off, reg->data); - } - + if (mask & 1) + nvkm_memx_wr32(ram->memx, reg->addr+off, reg->data); off += reg->stride; } } @@ -125,45 +122,45 @@ ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data) static inline void ramfuc_wait(struct ramfuc *ram, u32 addr, u32 mask, u32 data, u32 nsec) { - nouveau_memx_wait(ram->memx, addr, mask, data, nsec); + nvkm_memx_wait(ram->memx, addr, mask, data, nsec); } static inline void ramfuc_nsec(struct ramfuc *ram, u32 nsec) { - nouveau_memx_nsec(ram->memx, nsec); + nvkm_memx_nsec(ram->memx, nsec); } static inline void ramfuc_wait_vblank(struct ramfuc *ram) { - nouveau_memx_wait_vblank(ram->memx); + nvkm_memx_wait_vblank(ram->memx); } static inline void ramfuc_train(struct ramfuc *ram) { - nouveau_memx_train(ram->memx); + nvkm_memx_train(ram->memx); } static inline int -ramfuc_train_result(struct nouveau_fb *pfb, u32 *result, u32 rsize) +ramfuc_train_result(struct nvkm_fb *pfb, u32 *result, u32 rsize) { - struct nouveau_pmu *pmu = nouveau_pmu(pfb); + struct nvkm_pmu *pmu = nvkm_pmu(pfb); - return nouveau_memx_train_result(pmu, result, rsize); + return nvkm_memx_train_result(pmu, result, rsize); } static inline void ramfuc_block(struct ramfuc *ram) { - nouveau_memx_block(ram->memx); + nvkm_memx_block(ram->memx); } static inline void ramfuc_unblock(struct ramfuc *ram) { - nouveau_memx_unblock(ram->memx); + nvkm_memx_unblock(ram->memx); } #define ram_init(s,p) ramfuc_init(&(s)->base, (p)) @@ -180,5 +177,4 @@ ramfuc_unblock(struct ramfuc *ram) #define ram_train_result(s,r,l) ramfuc_train_result((s), (r), (l)) #define ram_block(s) ramfuc_block(&(s)->base) #define ram_unblock(s) ramfuc_unblock(&(s)->base) - #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c index d08eacd5..dcb175b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c @@ -21,23 +21,19 @@ * * Authors: Ben Skeggs */ +#include "gf100.h" +#include "ramfuc.h" +#include <core/option.h> #include <subdev/bios.h> #include <subdev/bios/pll.h> #include <subdev/bios/rammap.h> #include <subdev/bios/timing.h> -#include <subdev/ltc.h> - #include <subdev/clk.h> #include <subdev/clk/pll.h> +#include <subdev/ltc.h> -#include <core/option.h> - -#include "ramfuc.h" - -#include "nvc0.h" - -struct nvc0_ramfuc { +struct gf100_ramfuc { struct ramfuc base; struct ramfuc_reg r_0x10fe20; @@ -100,18 +96,18 @@ struct nvc0_ramfuc { struct ramfuc_reg r_0x13d8f4; }; -struct nvc0_ram { - struct nouveau_ram base; - struct nvc0_ramfuc fuc; +struct gf100_ram { + struct nvkm_ram base; + struct gf100_ramfuc fuc; struct nvbios_pll refpll; struct nvbios_pll mempll; }; static void -nvc0_ram_train(struct nvc0_ramfuc *fuc, u32 magic) +gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic) { - struct nvc0_ram *ram = container_of(fuc, typeof(*ram), fuc); - struct nouveau_fb *pfb = nouveau_fb(ram); + struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc); + struct nvkm_fb *pfb = nvkm_fb(ram); u32 part = nv_rd32(pfb, 0x022438), i; u32 mask = nv_rd32(pfb, 0x022554); u32 addr = 0x110974; @@ -127,12 +123,12 @@ nvc0_ram_train(struct nvc0_ramfuc *fuc, u32 magic) } static int -nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) +gf100_ram_calc(struct nvkm_fb *pfb, u32 freq) { - struct nouveau_clk *clk = nouveau_clk(pfb); - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nvc0_ram *ram = (void *)pfb->ram; - struct nvc0_ramfuc *fuc = &ram->fuc; + struct nvkm_clk *clk = nvkm_clk(pfb); + struct nvkm_bios *bios = nvkm_bios(pfb); + struct gf100_ram *ram = (void *)pfb->ram; + struct gf100_ramfuc *fuc = &ram->fuc; struct nvbios_ramcfg cfg; u8 ver, cnt, len, strap; struct { @@ -146,7 +142,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) /* lookup memory config data relevant to the target frequency */ rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, - &cnt, &ramcfg.size, &cfg); + &cnt, &ramcfg.size, &cfg); if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { nv_error(pfb, "invalid/missing rammap entry\n"); return -EINVAL; @@ -169,7 +165,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) strap = nv_ro08(bios, ramcfg.data + 0x01); if (strap != 0xff) { timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, - &cnt, &len); + &cnt, &len); if (!timing.data || ver != 0x10 || timing.size < 0x19) { nv_error(pfb, "invalid/missing timing entry\n"); return -EINVAL; @@ -213,8 +209,8 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) if (mode == 1 && from == 0) { /* calculate refpll */ - ret = nva3_pll_calc(nv_subdev(pfb), &ram->refpll, - ram->mempll.refclk, &N1, NULL, &M1, &P); + ret = gt215_pll_calc(nv_subdev(pfb), &ram->refpll, + ram->mempll.refclk, &N1, NULL, &M1, &P); if (ret <= 0) { nv_error(pfb, "unable to calc refpll\n"); return ret ? ret : -ERANGE; @@ -228,8 +224,8 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); /* calculate mempll */ - ret = nva3_pll_calc(nv_subdev(pfb), &ram->mempll, freq, - &N1, NULL, &M1, &P); + ret = gt215_pll_calc(nv_subdev(pfb), &ram->mempll, freq, + &N1, NULL, &M1, &P); if (ret <= 0) { nv_error(pfb, "unable to calc refpll\n"); return ret ? ret : -ERANGE; @@ -277,7 +273,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x10f210, 0x00000000); ram_nsec(fuc, 1000); if (mode == 0) - nvc0_ram_train(fuc, 0x000c1001); + gf100_ram_train(fuc, 0x000c1001); ram_wr32(fuc, 0x10f310, 0x00000001); ram_nsec(fuc, 1000); ram_wr32(fuc, 0x10f090, 0x00000061); @@ -325,8 +321,8 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x10f348, 0x00700008); ram_wr32(fuc, 0x61c140, 0x19240000); ram_wr32(fuc, 0x10f830, 0x00300017); - nvc0_ram_train(fuc, 0x80021001); - nvc0_ram_train(fuc, 0x80081001); + gf100_ram_train(fuc, 0x80021001); + gf100_ram_train(fuc, 0x80081001); ram_wr32(fuc, 0x10f340, 0x00500004); ram_nsec(fuc, 1000); ram_wr32(fuc, 0x10f830, 0x01300017); @@ -379,7 +375,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x13d8f4, 0x00000000); ram_wr32(fuc, 0x61c140, 0x09a40000); - nvc0_ram_train(fuc, 0x800e1008); + gf100_ram_train(fuc, 0x800e1008); ram_nsec(fuc, 1000); ram_wr32(fuc, 0x10f800, 0x00001804); @@ -392,7 +388,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_wr32(fuc, 0x10f9b0, 0x05313f41); ram_wr32(fuc, 0x10f9b4, 0x00002f50); - nvc0_ram_train(fuc, 0x010c1001); + gf100_ram_train(fuc, 0x010c1001); } ram_mask(fuc, 0x10f200, 0x00000800, 0x00000800); @@ -400,34 +396,35 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) if (mode == 0) ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); + return 0; } static int -nvc0_ram_prog(struct nouveau_fb *pfb) +gf100_ram_prog(struct nvkm_fb *pfb) { - struct nouveau_device *device = nv_device(pfb); - struct nvc0_ram *ram = (void *)pfb->ram; - struct nvc0_ramfuc *fuc = &ram->fuc; - ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", true)); + struct nvkm_device *device = nv_device(pfb); + struct gf100_ram *ram = (void *)pfb->ram; + struct gf100_ramfuc *fuc = &ram->fuc; + ram_exec(fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); return 0; } static void -nvc0_ram_tidy(struct nouveau_fb *pfb) +gf100_ram_tidy(struct nvkm_fb *pfb) { - struct nvc0_ram *ram = (void *)pfb->ram; - struct nvc0_ramfuc *fuc = &ram->fuc; + struct gf100_ram *ram = (void *)pfb->ram; + struct gf100_ramfuc *fuc = &ram->fuc; ram_exec(fuc, false); } -extern const u8 nvc0_pte_storage_type_map[256]; +extern const u8 gf100_pte_storage_type_map[256]; void -nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) +gf100_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem) { - struct nouveau_ltc *ltc = nouveau_ltc(pfb); - struct nouveau_mem *mem = *pmem; + struct nvkm_ltc *ltc = nvkm_ltc(pfb); + struct nvkm_mem *mem = *pmem; *pmem = NULL; if (unlikely(mem == NULL)) @@ -443,15 +440,15 @@ nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) } int -nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, - u32 memtype, struct nouveau_mem **pmem) +gf100_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, + u32 memtype, struct nvkm_mem **pmem) { - struct nouveau_mm *mm = &pfb->vram; - struct nouveau_mm_node *r; - struct nouveau_mem *mem; + struct nvkm_mm *mm = &pfb->vram; + struct nvkm_mm_node *r; + struct nvkm_mem *mem; int type = (memtype & 0x0ff); int back = (memtype & 0x800); - const bool comp = nvc0_pte_storage_type_map[type] != type; + const bool comp = gf100_pte_storage_type_map[type] != type; int ret; size >>= 12; @@ -469,7 +466,7 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, mutex_lock(&pfb->base.mutex); if (comp) { - struct nouveau_ltc *ltc = nouveau_ltc(pfb); + struct nvkm_ltc *ltc = nvkm_ltc(pfb); /* compression only works with lpages */ if (align == (1 << (17 - 12))) { @@ -478,15 +475,15 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, } if (unlikely(!mem->tag)) - type = nvc0_pte_storage_type_map[type]; + type = gf100_pte_storage_type_map[type]; } mem->memtype = type; do { if (back) - ret = nouveau_mm_tail(mm, 0, 1, size, ncmin, align, &r); + ret = nvkm_mm_tail(mm, 0, 1, size, ncmin, align, &r); else - ret = nouveau_mm_head(mm, 0, 1, size, ncmin, align, &r); + ret = nvkm_mm_head(mm, 0, 1, size, ncmin, align, &r); if (ret) { mutex_unlock(&pfb->base.mutex); pfb->ram->put(pfb, &mem); @@ -498,20 +495,20 @@ nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, } while (size); mutex_unlock(&pfb->base.mutex); - r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry); + r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry); mem->offset = (u64)r->offset << 12; *pmem = mem; return 0; } int -nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, u32 maskaddr, int size, - void **pobject) +gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, u32 maskaddr, int size, + void **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nouveau_ram *ram; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_bios *bios = nvkm_bios(pfb); + struct nvkm_ram *ram; const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ u32 parts = nv_rd32(pfb, 0x022438); @@ -521,7 +518,7 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, bool uniform = true; int ret, part; - ret = nouveau_ram_create_(parent, engine, oclass, size, pobject); + ret = nvkm_ram_create_(parent, engine, oclass, size, pobject); ram = *pobject; if (ret) return ret; @@ -529,7 +526,7 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, nv_debug(pfb, "0x100800: 0x%08x\n", nv_rd32(pfb, 0x100800)); nv_debug(pfb, "parts 0x%08x mask 0x%08x\n", parts, pmask); - ram->type = nouveau_fb_bios_memtype(bios); + ram->type = nvkm_fb_bios_memtype(bios); ram->ranks = (nv_rd32(pfb, 0x10f200) & 0x00000004) ? 2 : 1; /* read amount of vram attached to each memory controller */ @@ -551,11 +548,11 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, if (uniform) { offset = rsvd_head; length = (ram->size >> 12) - rsvd_head - rsvd_tail; - ret = nouveau_mm_init(&pfb->vram, offset, length, 1); + ret = nvkm_mm_init(&pfb->vram, offset, length, 1); } else { /* otherwise, address lowest common amount from 0GiB */ - ret = nouveau_mm_init(&pfb->vram, rsvd_head, - (bsize << 8) * parts - rsvd_head, 1); + ret = nvkm_mm_init(&pfb->vram, rsvd_head, + (bsize << 8) * parts - rsvd_head, 1); if (ret) return ret; @@ -563,27 +560,27 @@ nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, offset = (0x0200000000ULL >> 12) + (bsize << 8); length = (ram->size >> 12) - ((bsize * parts) << 8) - rsvd_tail; - ret = nouveau_mm_init(&pfb->vram, offset, length, 1); + ret = nvkm_mm_init(&pfb->vram, offset, length, 1); if (ret) - nouveau_mm_fini(&pfb->vram); + nvkm_mm_fini(&pfb->vram); } if (ret) return ret; - ram->get = nvc0_ram_get; - ram->put = nvc0_ram_put; + ram->get = gf100_ram_get; + ram->put = gf100_ram_put; return 0; } static int -nvc0_ram_init(struct nouveau_object *object) +gf100_ram_init(struct nvkm_object *object) { - struct nouveau_fb *pfb = (void *)object->parent; - struct nvc0_ram *ram = (void *)object; + struct nvkm_fb *pfb = (void *)object->parent; + struct gf100_ram *ram = (void *)object; int ret, i; - ret = nouveau_ram_init(&ram->base); + ret = nvkm_ram_init(&ram->base); if (ret) return ret; @@ -624,15 +621,15 @@ nvc0_ram_init(struct nouveau_object *object) } static int -nvc0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_bios *bios = nouveau_bios(parent); - struct nvc0_ram *ram; + struct nvkm_bios *bios = nvkm_bios(parent); + struct gf100_ram *ram; int ret; - ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram); + ret = gf100_ram_create(parent, engine, oclass, 0x022554, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -651,9 +648,9 @@ nvc0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, switch (ram->base.type) { case NV_MEM_TYPE_GDDR5: - ram->base.calc = nvc0_ram_calc; - ram->base.prog = nvc0_ram_prog; - ram->base.tidy = nvc0_ram_tidy; + ram->base.calc = gf100_ram_calc; + ram->base.prog = gf100_ram_prog; + ram->base.tidy = gf100_ram_tidy; break; default: nv_warn(ram, "reclocking of this ram type unsupported\n"); @@ -721,13 +718,13 @@ nvc0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass -nvc0_ram_oclass = { +struct nvkm_oclass +gf100_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_ram_ctor, - .dtor = _nouveau_ram_dtor, - .init = nvc0_ram_init, - .fini = _nouveau_ram_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_ram_ctor, + .dtor = _nvkm_ram_dtor, + .init = gf100_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c index 60050aa..97060cc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c @@ -21,29 +21,22 @@ * * Authors: Ben Skeggs */ +#include "ramfuc.h" +#include "gf100.h" -#include <subdev/gpio.h> - +#include <core/option.h> #include <subdev/bios.h> -#include <subdev/bios/pll.h> #include <subdev/bios/init.h> -#include <subdev/bios/rammap.h> -#include <subdev/bios/timing.h> #include <subdev/bios/M0205.h> #include <subdev/bios/M0209.h> - +#include <subdev/bios/pll.h> +#include <subdev/bios/rammap.h> +#include <subdev/bios/timing.h> #include <subdev/clk.h> #include <subdev/clk/pll.h> +#include <subdev/gpio.h> -#include <subdev/timer.h> - -#include <core/option.h> - -#include "nvc0.h" - -#include "ramfuc.h" - -struct nve0_ramfuc { +struct gk104_ramfuc { struct ramfuc base; struct nvbios_pll refpll; @@ -124,9 +117,9 @@ struct nve0_ramfuc { struct ramfuc_reg r_0x100750; }; -struct nve0_ram { - struct nouveau_ram base; - struct nve0_ramfuc fuc; +struct gk104_ram { + struct nvkm_ram base; + struct gk104_ramfuc fuc; struct list_head cfg; u32 parts; @@ -144,9 +137,9 @@ struct nve0_ram { * GDDR5 ******************************************************************************/ static void -nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data) +gk104_ram_train(struct gk104_ramfuc *fuc, u32 mask, u32 data) { - struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); + struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); u32 addr = 0x110974, i; ram_mask(fuc, 0x10f910, mask, data); @@ -160,9 +153,9 @@ nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data) } static void -r1373f4_init(struct nve0_ramfuc *fuc) +r1373f4_init(struct gk104_ramfuc *fuc) { - struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); + struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); const u32 runk0 = ram->fN1 << 16; @@ -210,10 +203,10 @@ r1373f4_init(struct nve0_ramfuc *fuc) } static void -r1373f4_fini(struct nve0_ramfuc *fuc) +r1373f4_fini(struct gk104_ramfuc *fuc) { - struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); - struct nouveau_ram_data *next = ram->base.next; + struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc); + struct nvkm_ram_data *next = ram->base.next; u8 v0 = next->bios.ramcfg_11_03_c0; u8 v1 = next->bios.ramcfg_11_03_30; u32 tmp; @@ -232,10 +225,10 @@ r1373f4_fini(struct nve0_ramfuc *fuc) } static void -nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg, - u32 _mask, u32 _data, u32 _copy) +gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg, + u32 _mask, u32 _data, u32 _copy) { - struct nve0_fb_priv *priv = (void *)nouveau_fb(ram); + struct gk104_fb_priv *priv = (void *)nvkm_fb(ram); struct ramfuc *fuc = &ram->fuc.base; u32 addr = 0x110000 + (reg->addr & 0xfff); u32 mask = _mask | _copy; @@ -246,19 +239,19 @@ nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg, if (ram->pnuts & (1 << i)) { u32 prev = nv_rd32(priv, addr); u32 next = (prev & ~mask) | data; - nouveau_memx_wr32(fuc->memx, addr, next); + nvkm_memx_wr32(fuc->memx, addr, next); } } } #define ram_nuts(s,r,m,d,c) \ - nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) + gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) static int -nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) +gk104_ram_calc_gddr5(struct nvkm_fb *pfb, u32 freq) { - struct nve0_ram *ram = (void *)pfb->ram; - struct nve0_ramfuc *fuc = &ram->fuc; - struct nouveau_ram_data *next = ram->base.next; + struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ramfuc *fuc = &ram->fuc; + struct nvkm_ram_data *next = ram->base.next; int vc = !next->bios.ramcfg_11_02_08; int mv = !next->bios.ramcfg_11_02_04; u32 mask, data; @@ -283,7 +276,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); - nve0_ram_train(fuc, 0x01020000, 0x000c0000); + gk104_ram_train(fuc, 0x01020000, 0x000c0000); ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ ram_nsec(fuc, 1000); @@ -588,7 +581,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) { u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); - nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ + gk104_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ ram_nsec(fuc, 1000); ram_wr32(fuc, 0x10f294, temp); } @@ -643,7 +636,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) } else { data = 0xa40e0000; } - nve0_ram_train(fuc, 0xbc0f0000, data); + gk104_ram_train(fuc, 0xbc0f0000, data); if (1) /* XXX: not always? */ ram_nsec(fuc, 1000); @@ -661,7 +654,7 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) } if (next->bios.ramcfg_11_07_02) - nve0_ram_train(fuc, 0x80020000, 0x01000000); + gk104_ram_train(fuc, 0x80020000, 0x01000000); ram_unblock(fuc); ram_wr32(fuc, 0x62c000, 0x0f0f0f00); @@ -680,14 +673,14 @@ nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) ******************************************************************************/ static int -nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) +gk104_ram_calc_sddr3(struct nvkm_fb *pfb, u32 freq) { - struct nve0_ram *ram = (void *)pfb->ram; - struct nve0_ramfuc *fuc = &ram->fuc; + struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ramfuc *fuc = &ram->fuc; const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); const u32 runk0 = ram->fN1 << 16; const u32 runk1 = ram->fN1; - struct nouveau_ram_data *next = ram->base.next; + struct nvkm_ram_data *next = ram->base.next; int vc = !next->bios.ramcfg_11_02_08; int mv = !next->bios.ramcfg_11_02_04; u32 mask, data; @@ -932,11 +925,10 @@ nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) ******************************************************************************/ static int -nve0_ram_calc_data(struct nouveau_fb *pfb, u32 khz, - struct nouveau_ram_data *data) +gk104_ram_calc_data(struct nvkm_fb *pfb, u32 khz, struct nvkm_ram_data *data) { - struct nve0_ram *ram = (void *)pfb->ram; - struct nouveau_ram_data *cfg; + struct gk104_ram *ram = (void *)pfb->ram; + struct nvkm_ram_data *cfg; u32 mhz = khz / 1000; list_for_each_entry(cfg, &ram->cfg, head) { @@ -953,10 +945,10 @@ nve0_ram_calc_data(struct nouveau_fb *pfb, u32 khz, } static int -nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) +gk104_ram_calc_xits(struct nvkm_fb *pfb, struct nvkm_ram_data *next) { - struct nve0_ram *ram = (void *)pfb->ram; - struct nve0_ramfuc *fuc = &ram->fuc; + struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ramfuc *fuc = &ram->fuc; int refclk, i; int ret; @@ -980,8 +972,8 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) refclk = fuc->mempll.refclk; /* calculate refpll coefficients */ - ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1, - &ram->fN1, &ram->M1, &ram->P1); + ret = gt215_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1, + &ram->fN1, &ram->M1, &ram->P1); fuc->mempll.refclk = ret; if (ret <= 0) { nv_error(pfb, "unable to calc refpll\n"); @@ -997,8 +989,8 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) fuc->mempll.min_p = 1; fuc->mempll.max_p = 2; - ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq, - &ram->N2, NULL, &ram->M2, &ram->P2); + ret = gt215_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq, + &ram->N2, NULL, &ram->M2, &ram->P2); if (ret <= 0) { nv_error(pfb, "unable to calc mempll\n"); return -EINVAL; @@ -1013,14 +1005,14 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) switch (ram->base.type) { case NV_MEM_TYPE_DDR3: - ret = nouveau_sddr3_calc(&ram->base); + ret = nvkm_sddr3_calc(&ram->base); if (ret == 0) - ret = nve0_ram_calc_sddr3(pfb, next->freq); + ret = gk104_ram_calc_sddr3(pfb, next->freq); break; case NV_MEM_TYPE_GDDR5: - ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0); + ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0); if (ret == 0) - ret = nve0_ram_calc_gddr5(pfb, next->freq); + ret = gk104_ram_calc_gddr5(pfb, next->freq); break; default: ret = -ENOSYS; @@ -1031,21 +1023,21 @@ nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) } static int -nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) +gk104_ram_calc(struct nvkm_fb *pfb, u32 freq) { - struct nouveau_clk *clk = nouveau_clk(pfb); - struct nve0_ram *ram = (void *)pfb->ram; - struct nouveau_ram_data *xits = &ram->base.xition; - struct nouveau_ram_data *copy; + struct nvkm_clk *clk = nvkm_clk(pfb); + struct gk104_ram *ram = (void *)pfb->ram; + struct nvkm_ram_data *xits = &ram->base.xition; + struct nvkm_ram_data *copy; int ret; if (ram->base.next == NULL) { - ret = nve0_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem), - &ram->base.former); + ret = gk104_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem), + &ram->base.former); if (ret) return ret; - ret = nve0_ram_calc_data(pfb, freq, &ram->base.target); + ret = gk104_ram_calc_data(pfb, freq, &ram->base.target); if (ret) return ret; @@ -1069,14 +1061,14 @@ nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) ram->base.next = &ram->base.target; } - return nve0_ram_calc_xits(pfb, ram->base.next); + return gk104_ram_calc_xits(pfb, ram->base.next); } static void -nve0_ram_prog_0(struct nouveau_fb *pfb, u32 freq) +gk104_ram_prog_0(struct nvkm_fb *pfb, u32 freq) { - struct nve0_ram *ram = (void *)pfb->ram; - struct nouveau_ram_data *cfg; + struct gk104_ram *ram = (void *)pfb->ram; + struct nvkm_ram_data *cfg; u32 mhz = freq / 1000; u32 mask, data; @@ -1149,35 +1141,35 @@ nve0_ram_prog_0(struct nouveau_fb *pfb, u32 freq) } static int -nve0_ram_prog(struct nouveau_fb *pfb) +gk104_ram_prog(struct nvkm_fb *pfb) { - struct nouveau_device *device = nv_device(pfb); - struct nve0_ram *ram = (void *)pfb->ram; - struct nve0_ramfuc *fuc = &ram->fuc; - struct nouveau_ram_data *next = ram->base.next; + struct nvkm_device *device = nv_device(pfb); + struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ramfuc *fuc = &ram->fuc; + struct nvkm_ram_data *next = ram->base.next; - if (!nouveau_boolopt(device->cfgopt, "NvMemExec", true)) { + if (!nvkm_boolopt(device->cfgopt, "NvMemExec", true)) { ram_exec(fuc, false); return (ram->base.next == &ram->base.xition); } - nve0_ram_prog_0(pfb, 1000); + gk104_ram_prog_0(pfb, 1000); ram_exec(fuc, true); - nve0_ram_prog_0(pfb, next->freq); + gk104_ram_prog_0(pfb, next->freq); return (ram->base.next == &ram->base.xition); } static void -nve0_ram_tidy(struct nouveau_fb *pfb) +gk104_ram_tidy(struct nvkm_fb *pfb) { - struct nve0_ram *ram = (void *)pfb->ram; - struct nve0_ramfuc *fuc = &ram->fuc; + struct gk104_ram *ram = (void *)pfb->ram; + struct gk104_ramfuc *fuc = &ram->fuc; ram->base.next = NULL; ram_exec(fuc, false); } -struct nve0_ram_train { +struct gk104_ram_train { u16 mask; struct nvbios_M0209S remap; struct nvbios_M0209S type00; @@ -1190,10 +1182,10 @@ struct nve0_ram_train { }; static int -nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg, - struct nve0_ram_train *train) +gk104_ram_train_type(struct nvkm_fb *pfb, int i, u8 ramcfg, + struct gk104_ram_train *train) { - struct nouveau_bios *bios = nouveau_bios(pfb); + struct nvkm_bios *bios = nvkm_bios(pfb); struct nvbios_M0205E M0205E; struct nvbios_M0205S M0205S; struct nvbios_M0209E M0209E; @@ -1251,7 +1243,7 @@ nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg, } static int -nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train) +gk104_ram_train_init_0(struct nvkm_fb *pfb, struct gk104_ram_train *train) { int i, j; @@ -1285,15 +1277,15 @@ nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train) } static int -nve0_ram_train_init(struct nouveau_fb *pfb) +gk104_ram_train_init(struct nvkm_fb *pfb) { u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb)); - struct nve0_ram_train *train; + struct gk104_ram_train *train; int ret = -ENOMEM, i; if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) { for (i = 0; i < 0x100; i++) { - ret = nve0_ram_train_type(pfb, i, ramcfg, train); + ret = gk104_ram_train_type(pfb, i, ramcfg, train); if (ret && ret != -ENOENT) break; } @@ -1301,7 +1293,7 @@ nve0_ram_train_init(struct nouveau_fb *pfb) switch (pfb->ram->type) { case NV_MEM_TYPE_GDDR5: - ret = nve0_ram_train_init_0(pfb, train); + ret = gk104_ram_train_init_0(pfb, train); break; default: ret = 0; @@ -1313,16 +1305,16 @@ nve0_ram_train_init(struct nouveau_fb *pfb) } int -nve0_ram_init(struct nouveau_object *object) +gk104_ram_init(struct nvkm_object *object) { - struct nouveau_fb *pfb = (void *)object->parent; - struct nve0_ram *ram = (void *)object; - struct nouveau_bios *bios = nouveau_bios(pfb); + struct nvkm_fb *pfb = (void *)object->parent; + struct gk104_ram *ram = (void *)object; + struct nvkm_bios *bios = nvkm_bios(pfb); u8 ver, hdr, cnt, len, snr, ssz; u32 data, save; int ret, i; - ret = nouveau_ram_init(&ram->base); + ret = nvkm_ram_init(&ram->base); if (ret) return ret; @@ -1360,15 +1352,15 @@ nve0_ram_init(struct nouveau_object *object) nv_wr32(pfb, 0x10ecc0, 0xffffffff); nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010); - return nve0_ram_train_init(pfb); + return gk104_ram_train_init(pfb); } static int -nve0_ram_ctor_data(struct nve0_ram *ram, u8 ramcfg, int i) +gk104_ram_ctor_data(struct gk104_ram *ram, u8 ramcfg, int i) { - struct nouveau_fb *pfb = (void *)nv_object(ram)->parent; - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nouveau_ram_data *cfg; + struct nvkm_fb *pfb = (void *)nv_object(ram)->parent; + struct nvkm_bios *bios = nvkm_bios(pfb); + struct nvkm_ram_data *cfg; struct nvbios_ramcfg *d = &ram->diff; struct nvbios_ramcfg *p, *n; u8 ver, hdr, cnt, len; @@ -1434,33 +1426,33 @@ done: } static void -nve0_ram_dtor(struct nouveau_object *object) +gk104_ram_dtor(struct nvkm_object *object) { - struct nve0_ram *ram = (void *)object; - struct nouveau_ram_data *cfg, *tmp; + struct gk104_ram *ram = (void *)object; + struct nvkm_ram_data *cfg, *tmp; list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) { kfree(cfg); } - nouveau_ram_destroy(&ram->base); + nvkm_ram_destroy(&ram->base); } static int -nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nouveau_gpio *gpio = nouveau_gpio(pfb); + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_bios *bios = nvkm_bios(pfb); + struct nvkm_gpio *gpio = nvkm_gpio(pfb); struct dcb_gpio_func func; - struct nve0_ram *ram; + struct gk104_ram *ram; int ret, i; u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb)); u32 tmp; - ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram); + ret = gf100_ram_create(parent, engine, oclass, 0x022554, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -1470,9 +1462,9 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, switch (ram->base.type) { case NV_MEM_TYPE_DDR3: case NV_MEM_TYPE_GDDR5: - ram->base.calc = nve0_ram_calc; - ram->base.prog = nve0_ram_prog; - ram->base.tidy = nve0_ram_tidy; + ram->base.calc = gk104_ram_calc; + ram->base.prog = gk104_ram_prog; + ram->base.tidy = gk104_ram_tidy; break; default: nv_warn(pfb, "reclocking of this RAM type is unsupported\n"); @@ -1510,7 +1502,7 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, * need to treat this condition as a "don't touch" indicator. */ for (i = 0; !ret; i++) { - ret = nve0_ram_ctor_data(ram, ramcfg, i); + ret = gk104_ram_ctor_data(ram, ramcfg, i); if (ret && ret != -ENOENT) { nv_error(pfb, "failed to parse ramcfg data\n"); return ret; @@ -1634,13 +1626,13 @@ nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass -nve0_ram_oclass = { +struct nvkm_oclass +gk104_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_ram_ctor, - .dtor = nve0_ram_dtor, - .init = nve0_ram_init, - .fini = _nouveau_ram_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gk104_ram_ctor, + .dtor = gk104_ram_dtor, + .init = gk104_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c index 4d77d75..6cf526b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c @@ -19,20 +19,17 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ - #include "priv.h" -#include <subdev/fb.h> - struct gk20a_mem { - struct nouveau_mem base; + struct nvkm_mem base; void *cpuaddr; dma_addr_t handle; }; #define to_gk20a_mem(m) container_of(m, struct gk20a_mem, base) static void -gk20a_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) +gk20a_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem) { struct device *dev = nv_device_base(nv_device(pfb)); struct gk20a_mem *mem = to_gk20a_mem(*pmem); @@ -50,8 +47,8 @@ gk20a_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) } static int -gk20a_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, - u32 memtype, struct nouveau_mem **pmem) +gk20a_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, + u32 memtype, struct nvkm_mem **pmem) { struct device *dev = nv_device_base(nv_device(pfb)); struct gk20a_mem *mem; @@ -116,19 +113,18 @@ gk20a_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, mem->base.pages[i] = mem->handle + (PAGE_SIZE * i); mem->base.offset = (u64)mem->base.pages[0]; - return 0; } static int -gk20a_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 datasize, - struct nouveau_object **pobject) +gk20a_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 datasize, + struct nvkm_object **pobject) { - struct nouveau_ram *ram; + struct nvkm_ram *ram; int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -137,16 +133,15 @@ gk20a_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ram->get = gk20a_ram_get; ram->put = gk20a_ram_put; - return 0; } -struct nouveau_oclass +struct nvkm_oclass gk20a_ram_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gk20a_ram_ctor, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c index 4c63635..a298b39 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.c @@ -21,22 +21,21 @@ * * Authors: Ben Skeggs */ - -#include "nvc0.h" +#include "gf100.h" struct gm107_ram { - struct nouveau_ram base; + struct nvkm_ram base; }; static int -gm107_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gm107_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct gm107_ram *ram; int ret; - ret = nvc0_ram_create(parent, engine, oclass, 0x021c14, &ram); + ret = gf100_ram_create(parent, engine, oclass, 0x021c14, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -44,13 +43,13 @@ gm107_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass gm107_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = gm107_ram_ctor, - .dtor = _nouveau_ram_dtor, - .init = nve0_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = gk104_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c index f3cc7a1..692a1cc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c @@ -23,32 +23,21 @@ * Roy Spliet <rspliet@eclipso.eu> */ +#include "ramfuc.h" +#include "nv50.h" + +#include <core/option.h> #include <subdev/bios.h> -#include <subdev/bios/bit.h> -#include <subdev/bios/pll.h> -#include <subdev/bios/rammap.h> #include <subdev/bios/M0205.h> +#include <subdev/bios/rammap.h> #include <subdev/bios/timing.h> - #include <subdev/clk/gt215.h> -#include <subdev/clk/pll.h> - #include <subdev/gpio.h> -#include <subdev/timer.h> - -#include <engine/fifo.h> - -#include <core/option.h> - -#include "ramfuc.h" - -#include "nv50.h" - /* XXX: Remove when memx gains GPIO support */ extern int nv50_gpio_location(int line, u32 *reg, u32 *shift); -struct nva3_ramfuc { +struct gt215_ramfuc { struct ramfuc base; struct ramfuc_reg r_0x001610; struct ramfuc_reg r_0x001700; @@ -89,7 +78,7 @@ struct nva3_ramfuc { struct ramfuc_reg r_gpioFBVREF; }; -struct nva3_ltrain { +struct gt215_ltrain { enum { NVA3_TRAIN_UNKNOWN, NVA3_TRAIN_UNSUPPORTED, @@ -100,17 +89,17 @@ struct nva3_ltrain { u32 r_100720; u32 r_1111e0; u32 r_111400; - struct nouveau_mem *mem; + struct nvkm_mem *mem; }; -struct nva3_ram { - struct nouveau_ram base; - struct nva3_ramfuc fuc; - struct nva3_ltrain ltrain; +struct gt215_ram { + struct nvkm_ram base; + struct gt215_ramfuc fuc; + struct gt215_ltrain ltrain; }; void -nva3_link_train_calc(u32 *vals, struct nva3_ltrain *train) +gt215_link_train_calc(u32 *vals, struct gt215_ltrain *train) { int i, lo, hi; u8 median[8], bins[4] = {0, 0, 0, 0}, bin = 0, qty = 0; @@ -164,14 +153,14 @@ nva3_link_train_calc(u32 *vals, struct nva3_ltrain *train) * Link training for (at least) DDR3 */ int -nva3_link_train(struct nouveau_fb *pfb) +gt215_link_train(struct nvkm_fb *pfb) { - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nva3_ram *ram = (void *)pfb->ram; - struct nouveau_clk *clk = nouveau_clk(pfb); - struct nva3_ltrain *train = &ram->ltrain; - struct nouveau_device *device = nv_device(pfb); - struct nva3_ramfuc *fuc = &ram->fuc; + struct nvkm_bios *bios = nvkm_bios(pfb); + struct gt215_ram *ram = (void *)pfb->ram; + struct nvkm_clk *clk = nvkm_clk(pfb); + struct gt215_ltrain *train = &ram->ltrain; + struct nvkm_device *device = nv_device(pfb); + struct gt215_ramfuc *fuc = &ram->fuc; u32 *result, r1700; int ret, i; struct nvbios_M0205T M0205T = { 0 }; @@ -180,7 +169,7 @@ nva3_link_train(struct nouveau_fb *pfb) unsigned long flags; unsigned long *f = &flags; - if (nouveau_boolopt(device->cfgopt, "NvMemExec", true) != true) + if (nvkm_boolopt(device->cfgopt, "NvMemExec", true) != true) return -ENOSYS; /* XXX: Multiple partitions? */ @@ -197,7 +186,7 @@ nva3_link_train(struct nouveau_fb *pfb) clk_current = clk->read(clk, nv_clk_src_mem); - ret = nva3_clk_pre(clk, f); + ret = gt215_clk_pre(clk, f); if (ret) goto out; @@ -252,12 +241,12 @@ nva3_link_train(struct nouveau_fb *pfb) nv_mask(pfb, 0x616308, 0x10, 0x10); nv_mask(pfb, 0x616b08, 0x10, 0x10); - nva3_clk_post(clk, f); + gt215_clk_post(clk, f); ram_train_result(pfb, result, 64); for (i = 0; i < 64; i++) nv_debug(pfb, "Train: %08x", result[i]); - nva3_link_train_calc(result, train); + gt215_link_train_calc(result, train); nv_debug(pfb, "Train: %08x %08x %08x", train->r_100720, train->r_1111e0, train->r_111400); @@ -274,12 +263,12 @@ out: train->state = NVA3_TRAIN_UNSUPPORTED; - nva3_clk_post(clk, f); + gt215_clk_post(clk, f); return ret; } int -nva3_link_train_init(struct nouveau_fb *pfb) +gt215_link_train_init(struct nvkm_fb *pfb) { static const u32 pattern[16] = { 0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee, @@ -287,10 +276,10 @@ nva3_link_train_init(struct nouveau_fb *pfb) 0x33333333, 0x55555555, 0x77777777, 0x66666666, 0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb, }; - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nva3_ram *ram = (void *)pfb->ram; - struct nva3_ltrain *train = &ram->ltrain; - struct nouveau_mem *mem; + struct nvkm_bios *bios = nvkm_bios(pfb); + struct gt215_ram *ram = (void *)pfb->ram; + struct gt215_ltrain *train = &ram->ltrain; + struct nvkm_mem *mem; struct nvbios_M0205E M0205E; u8 ver, hdr, cnt, len; u32 r001700; @@ -340,14 +329,13 @@ nva3_link_train_init(struct nouveau_fb *pfb) train->r_100720 = nv_rd32(pfb, 0x100720); train->r_1111e0 = nv_rd32(pfb, 0x1111e0); train->r_111400 = nv_rd32(pfb, 0x111400); - return 0; } void -nva3_link_train_fini(struct nouveau_fb *pfb) +gt215_link_train_fini(struct nvkm_fb *pfb) { - struct nva3_ram *ram = (void *)pfb->ram; + struct gt215_ram *ram = (void *)pfb->ram; if (ram->ltrain.mem) pfb->ram->put(pfb, &ram->ltrain.mem); @@ -358,9 +346,9 @@ nva3_link_train_fini(struct nouveau_fb *pfb) */ #define T(t) cfg->timing_10_##t static int -nva3_ram_timing_calc(struct nouveau_fb *pfb, u32 *timing) +gt215_ram_timing_calc(struct nvkm_fb *pfb, u32 *timing) { - struct nva3_ram *ram = (void *)pfb->ram; + struct gt215_ram *ram = (void *)pfb->ram; struct nvbios_ramcfg *cfg = &ram->base.target.bios; int tUNK_base, tUNK_40_0, prevCL; u32 cur2, cur3, cur7, cur8; @@ -433,7 +421,7 @@ nva3_ram_timing_calc(struct nouveau_fb *pfb, u32 *timing) #undef T static void -nouveau_sddr2_dll_reset(struct nva3_ramfuc *fuc) +nvkm_sddr2_dll_reset(struct gt215_ramfuc *fuc) { ram_mask(fuc, mr[0], 0x100, 0x100); ram_nsec(fuc, 1000); @@ -442,7 +430,7 @@ nouveau_sddr2_dll_reset(struct nva3_ramfuc *fuc) } static void -nouveau_sddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr) +nvkm_sddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr) { u32 mr1_old = ram_rd32(fuc, mr[1]); @@ -454,7 +442,7 @@ nouveau_sddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr) } static void -nouveau_gddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr) +nvkm_gddr3_dll_disable(struct gt215_ramfuc *fuc, u32 *mr) { u32 mr1_old = ram_rd32(fuc, mr[1]); @@ -465,7 +453,7 @@ nouveau_gddr3_dll_disable(struct nva3_ramfuc *fuc, u32 *mr) } static void -nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clk_info *mclk) +gt215_ram_lock_pll(struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk) { ram_wr32(fuc, 0x004004, mclk->pll); ram_mask(fuc, 0x004000, 0x00000001, 0x00000001); @@ -475,9 +463,9 @@ nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clk_info *mclk) } static void -nva3_ram_fbvref(struct nva3_ramfuc *fuc, u32 val) +gt215_ram_fbvref(struct gt215_ramfuc *fuc, u32 val) { - struct nouveau_gpio *gpio = nouveau_gpio(fuc->base.pfb); + struct nvkm_gpio *gpio = nvkm_gpio(fuc->base.pfb); struct dcb_gpio_func func; u32 reg, sh, gpio_val; int ret; @@ -498,14 +486,14 @@ nva3_ram_fbvref(struct nva3_ramfuc *fuc, u32 val) } static int -nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) +gt215_ram_calc(struct nvkm_fb *pfb, u32 freq) { - struct nouveau_bios *bios = nouveau_bios(pfb); - struct nva3_ram *ram = (void *)pfb->ram; - struct nva3_ramfuc *fuc = &ram->fuc; - struct nva3_ltrain *train = &ram->ltrain; - struct nva3_clk_info mclk; - struct nouveau_ram_data *next; + struct nvkm_bios *bios = nvkm_bios(pfb); + struct gt215_ram *ram = (void *)pfb->ram; + struct gt215_ramfuc *fuc = &ram->fuc; + struct gt215_ltrain *train = &ram->ltrain; + struct gt215_clk_info mclk; + struct nvkm_ram_data *next; u8 ver, hdr, cnt, len, strap; u32 data; u32 r004018, r100760, r100da0, r111100, ctrl; @@ -519,12 +507,12 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) ram->base.next = next; if (ram->ltrain.state == NVA3_TRAIN_ONCE) - nva3_link_train(pfb); + gt215_link_train(pfb); /* lookup memory config data relevant to the target frequency */ i = 0; data = nvbios_rammapEm(bios, freq / 1000, &ver, &hdr, &cnt, &len, - &next->bios); + &next->bios); if (!data || ver != 0x10 || hdr < 0x05) { nv_error(pfb, "invalid/missing rammap entry\n"); return -EINVAL; @@ -555,13 +543,13 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) } } - ret = nva3_pll_info(nouveau_clk(pfb), 0x12, 0x4000, freq, &mclk); + ret = gt215_pll_info(nvkm_clk(pfb), 0x12, 0x4000, freq, &mclk); if (ret < 0) { nv_error(pfb, "failed mclk calculation\n"); return ret; } - nva3_ram_timing_calc(pfb, timing); + gt215_ram_timing_calc(pfb, timing); ret = ram_init(fuc, pfb); if (ret) @@ -574,13 +562,13 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) switch (ram->base.type) { case NV_MEM_TYPE_DDR2: - ret = nouveau_sddr2_calc(&ram->base); + ret = nvkm_sddr2_calc(&ram->base); break; case NV_MEM_TYPE_DDR3: - ret = nouveau_sddr3_calc(&ram->base); + ret = nvkm_sddr3_calc(&ram->base); break; case NV_MEM_TYPE_GDDR3: - ret = nouveau_gddr3_calc(&ram->base); + ret = nvkm_gddr3_calc(&ram->base); break; default: ret = -ENOSYS; @@ -621,7 +609,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) /* If switching from non-pll to pll, lock before disabling FB */ if (mclk.pll && !pll2pll) { ram_mask(fuc, 0x004128, 0x003f3141, mclk.clk | 0x00000101); - nva3_ram_lock_pll(fuc, &mclk); + gt215_ram_lock_pll(fuc, &mclk); } /* Start with disabling some CRTCs and PFIFO? */ @@ -643,15 +631,15 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) /* If we're disabling the DLL, do it now */ switch (next->bios.ramcfg_10_DLLoff * ram->base.type) { case NV_MEM_TYPE_DDR3: - nouveau_sddr3_dll_disable(fuc, ram->base.mr); + nvkm_sddr3_dll_disable(fuc, ram->base.mr); break; case NV_MEM_TYPE_GDDR3: - nouveau_gddr3_dll_disable(fuc, ram->base.mr); + nvkm_gddr3_dll_disable(fuc, ram->base.mr); break; } if (fuc->r_gpioFBVREF.addr && next->bios.timing_10_ODT) - nva3_ram_fbvref(fuc, 0); + gt215_ram_fbvref(fuc, 0); /* Brace RAM for impact */ ram_wr32(fuc, 0x1002d4, 0x00000001); @@ -678,7 +666,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x004000, 0x00000008, 0x00000008); ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000); ram_wr32(fuc, 0x004018, 0x00001000); - nva3_ram_lock_pll(fuc, &mclk); + gt215_ram_lock_pll(fuc, &mclk); } if (mclk.pll) { @@ -818,11 +806,11 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) ram_mask(fuc, 0x111100, 0xffffffff, r111100); if (fuc->r_gpioFBVREF.addr && !next->bios.timing_10_ODT) - nva3_ram_fbvref(fuc, 1); + gt215_ram_fbvref(fuc, 1); /* Reset DLL */ if (!next->bios.ramcfg_10_DLLoff) - nouveau_sddr2_dll_reset(fuc); + nvkm_sddr2_dll_reset(fuc); if (ram->base.type == NV_MEM_TYPE_GDDR3) { ram_nsec(fuc, 31000); @@ -866,12 +854,12 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) } static int -nva3_ram_prog(struct nouveau_fb *pfb) +gt215_ram_prog(struct nvkm_fb *pfb) { - struct nouveau_device *device = nv_device(pfb); - struct nva3_ram *ram = (void *)pfb->ram; - struct nva3_ramfuc *fuc = &ram->fuc; - bool exec = nouveau_boolopt(device->cfgopt, "NvMemExec", true); + struct nvkm_device *device = nv_device(pfb); + struct gt215_ram *ram = (void *)pfb->ram; + struct gt215_ramfuc *fuc = &ram->fuc; + bool exec = nvkm_boolopt(device->cfgopt, "NvMemExec", true); if (exec) { nv_mask(pfb, 0x001534, 0x2, 0x2); @@ -891,49 +879,48 @@ nva3_ram_prog(struct nouveau_fb *pfb) } static void -nva3_ram_tidy(struct nouveau_fb *pfb) +gt215_ram_tidy(struct nvkm_fb *pfb) { - struct nva3_ram *ram = (void *)pfb->ram; - struct nva3_ramfuc *fuc = &ram->fuc; + struct gt215_ram *ram = (void *)pfb->ram; + struct gt215_ramfuc *fuc = &ram->fuc; ram_exec(fuc, false); } static int -nva3_ram_init(struct nouveau_object *object) +gt215_ram_init(struct nvkm_object *object) { - struct nouveau_fb *pfb = (void *)object->parent; - struct nva3_ram *ram = (void *)object; + struct nvkm_fb *pfb = (void *)object->parent; + struct gt215_ram *ram = (void *)object; int ret; - ret = nouveau_ram_init(&ram->base); + ret = nvkm_ram_init(&ram->base); if (ret) return ret; - nva3_link_train_init(pfb); - + gt215_link_train_init(pfb); return 0; } static int -nva3_ram_fini(struct nouveau_object *object, bool suspend) +gt215_ram_fini(struct nvkm_object *object, bool suspend) { - struct nouveau_fb *pfb = (void *)object->parent; + struct nvkm_fb *pfb = (void *)object->parent; if (!suspend) - nva3_link_train_fini(pfb); + gt215_link_train_fini(pfb); return 0; } static int -nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 datasize, - struct nouveau_object **pobject) +gt215_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 datasize, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_gpio *gpio = nouveau_gpio(pfb); + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_gpio *gpio = nvkm_gpio(pfb); struct dcb_gpio_func func; - struct nva3_ram *ram; + struct gt215_ram *ram; int ret, i; u32 reg, shift; @@ -946,9 +933,9 @@ nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, case NV_MEM_TYPE_DDR2: case NV_MEM_TYPE_DDR3: case NV_MEM_TYPE_GDDR3: - ram->base.calc = nva3_ram_calc; - ram->base.prog = nva3_ram_prog; - ram->base.tidy = nva3_ram_tidy; + ram->base.calc = gt215_ram_calc; + ram->base.prog = gt215_ram_prog; + ram->base.tidy = gt215_ram_tidy; break; default: nv_warn(ram, "reclocking of this ram type unsupported\n"); @@ -1013,12 +1000,12 @@ nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass -nva3_ram_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nva3_ram_ctor, - .dtor = _nouveau_ram_dtor, - .init = nva3_ram_init, - .fini = nva3_ram_fini, +struct nvkm_oclass +gt215_ram_oclass = { + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gt215_ram_ctor, + .dtor = _nvkm_ram_dtor, + .init = gt215_ram_init, + .fini = gt215_ram_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c index 033a8e9..abc18e8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvaa.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c @@ -21,26 +21,25 @@ * * Authors: Ben Skeggs */ - #include "nv50.h" -struct nvaa_ram_priv { - struct nouveau_ram base; +struct mcp77_ram_priv { + struct nvkm_ram base; u64 poller_base; }; static int -nvaa_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 datasize, - struct nouveau_object **pobject) +mcp77_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 datasize, + struct nvkm_object **pobject) { u32 rsvd_head = ( 256 * 1024); /* vga memory */ u32 rsvd_tail = (1024 * 1024); /* vbios etc */ - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nvaa_ram_priv *priv; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct mcp77_ram_priv *priv; int ret; - ret = nouveau_ram_create(parent, engine, oclass, &priv); + ret = nvkm_ram_create(parent, engine, oclass, &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -52,9 +51,9 @@ nvaa_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, rsvd_tail += 0x1000; priv->poller_base = priv->base.size - rsvd_tail; - ret = nouveau_mm_init(&pfb->vram, rsvd_head >> 12, - (priv->base.size - (rsvd_head + rsvd_tail)) >> 12, - 1); + ret = nvkm_mm_init(&pfb->vram, rsvd_head >> 12, + (priv->base.size - (rsvd_head + rsvd_tail)) >> 12, + 1); if (ret) return ret; @@ -64,14 +63,14 @@ nvaa_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } static int -nvaa_ram_init(struct nouveau_object *object) +mcp77_ram_init(struct nvkm_object *object) { - struct nouveau_fb *pfb = nouveau_fb(object); - struct nvaa_ram_priv *priv = (void *)object; + struct nvkm_fb *pfb = nvkm_fb(object); + struct mcp77_ram_priv *priv = (void *)object; int ret; u64 dniso, hostnb, flush; - ret = nouveau_ram_init(&priv->base); + ret = nvkm_ram_init(&priv->base); if (ret) return ret; @@ -88,16 +87,15 @@ nvaa_ram_init(struct nouveau_object *object) nv_mask(pfb, 0x100c14, 0x00000000, 0x00000002); nv_wr32(pfb, 0x100c24, flush); nv_mask(pfb, 0x100c14, 0x00000000, 0x00010000); - return 0; } -struct nouveau_oclass -nvaa_ram_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvaa_ram_ctor, - .dtor = _nouveau_ram_dtor, - .init = nvaa_ram_init, - .fini = _nouveau_ram_fini, +struct nvkm_oclass +mcp77_ram_oclass = { + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = mcp77_ram_ctor, + .dtor = _nvkm_ram_dtor, + .init = mcp77_ram_init, + .fini = _nvkm_ram_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c index 1972268..855de16 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c @@ -21,22 +21,20 @@ * * Authors: Ben Skeggs */ - -#include <subdev/fb/regsnv04.h> - #include "priv.h" +#include "regsnv04.h" static int -nv04_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_ram *ram; u32 boot0 = nv_rd32(pfb, NV04_PFB_BOOT_0); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -65,16 +63,17 @@ nv04_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, ram->type = NV_MEM_TYPE_SGRAM; else ram->type = NV_MEM_TYPE_SDRAM; + return 0; } -struct nouveau_oclass +struct nvkm_oclass nv04_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c index 8311f37..3b8a1ed 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs */ - #include "priv.h" static int -nv10_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_ram *ram; u32 cfg0 = nv_rd32(pfb, 0x100200); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -48,14 +47,13 @@ nv10_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } - -struct nouveau_oclass +struct nvkm_oclass nv10_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv10_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c index d0caddf..8bb7e43 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c @@ -21,16 +21,15 @@ * * Authors: Ben Skeggs */ - #include "priv.h" static int -nv1a_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_ram *ram; struct pci_dev *bridge; u32 mem, mib; int ret; @@ -41,7 +40,7 @@ nv1a_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return -ENODEV; } - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -59,13 +58,13 @@ nv1a_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv1a_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv1a_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c index fdc11bb..d9e7187 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs */ - #include "priv.h" static int -nv20_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_ram *ram; u32 pbus1218 = nv_rd32(pfb, 0x001218); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -51,13 +50,13 @@ nv20_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv20_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv20_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c index 50cbc38..a36a90c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c @@ -21,23 +21,19 @@ * * Authors: Ben Skeggs */ +#include "nv40.h" #include <subdev/bios.h> #include <subdev/bios/bit.h> -#include <subdev/bios/pll.h> #include <subdev/bios/init.h> -#include <subdev/clk.h> +#include <subdev/bios/pll.h> #include <subdev/clk/pll.h> #include <subdev/timer.h> -#include <engine/fifo.h> - -#include "nv40.h" - int -nv40_ram_calc(struct nouveau_fb *pfb, u32 freq) +nv40_ram_calc(struct nvkm_fb *pfb, u32 freq) { - struct nouveau_bios *bios = nouveau_bios(pfb); + struct nvkm_bios *bios = nvkm_bios(pfb); struct nv40_ram *ram = (void *)pfb->ram; struct nvbios_pll pll; int N1, M1, N2, M2; @@ -68,9 +64,9 @@ nv40_ram_calc(struct nouveau_fb *pfb, u32 freq) } int -nv40_ram_prog(struct nouveau_fb *pfb) +nv40_ram_prog(struct nvkm_fb *pfb) { - struct nouveau_bios *bios = nouveau_bios(pfb); + struct nvkm_bios *bios = nvkm_bios(pfb); struct nv40_ram *ram = (void *)pfb->ram; struct bit_entry M; u32 crtc_mask = 0; @@ -167,21 +163,21 @@ nv40_ram_prog(struct nouveau_fb *pfb) } void -nv40_ram_tidy(struct nouveau_fb *pfb) +nv40_ram_tidy(struct nvkm_fb *pfb) { } static int -nv40_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); struct nv40_ram *ram; u32 pbus1218 = nv_rd32(pfb, 0x001218); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -203,13 +199,13 @@ nv40_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, } -struct nouveau_oclass +struct nvkm_oclass nv40_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv40_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c index d64498a..33c612b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs */ - #include "nv40.h" static int -nv41_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); struct nv40_ram *ram; u32 pfb474 = nv_rd32(pfb, 0x100474); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -55,13 +54,13 @@ nv41_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv41_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv41_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c index 089acac..f575a72 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs */ - #include "nv40.h" static int -nv44_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); struct nv40_ram *ram; u32 pfb474 = nv_rd32(pfb, 0x100474); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -53,13 +52,13 @@ nv44_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv44_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv44_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c index baa013a..51b44cd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c @@ -21,20 +21,19 @@ * * Authors: Ben Skeggs */ - #include "nv40.h" static int -nv49_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); struct nv40_ram *ram; u32 pfb914 = nv_rd32(pfb, 0x100914); int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -55,13 +54,13 @@ nv49_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv49_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv49_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c index 63a6aab..f3ed1c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c @@ -21,19 +21,18 @@ * * Authors: Ben Skeggs */ - #include "priv.h" static int -nv4e_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_ram *ram; int ret; - ret = nouveau_ram_create(parent, engine, oclass, &ram); + ret = nvkm_ram_create(parent, engine, oclass, &ram); *pobject = nv_object(ram); if (ret) return ret; @@ -43,13 +42,13 @@ nv4e_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv4e_ram_oclass = { .handle = 0, - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv4e_ram_create, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c index 8d2970c..14f5ba5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c @@ -21,21 +21,15 @@ * * Authors: Ben Skeggs */ +#include "nv50.h" +#include "ramseq.h" +#include <core/option.h> #include <subdev/bios.h> -#include <subdev/bios/bit.h> -#include <subdev/bios/pll.h> #include <subdev/bios/perf.h> +#include <subdev/bios/pll.h> #include <subdev/bios/timing.h> #include <subdev/clk/pll.h> -#include <subdev/fb.h> - -#include <core/option.h> -#include <core/mm.h> - -#include "ramseq.h" - -#include "nv50.h" struct nv50_ramseq { struct hwsq base; @@ -56,16 +50,16 @@ struct nv50_ramseq { }; struct nv50_ram { - struct nouveau_ram base; + struct nvkm_ram base; struct nv50_ramseq hwsq; }; #define QFX5800NVA0 1 static int -nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) +nv50_ram_calc(struct nvkm_fb *pfb, u32 freq) { - struct nouveau_bios *bios = nouveau_bios(pfb); + struct nvkm_bios *bios = nvkm_bios(pfb); struct nv50_ram *ram = (void *)pfb->ram; struct nv50_ramseq *hwsq = &ram->hwsq; struct nvbios_perfE perfE; @@ -82,7 +76,7 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) i = 0; do { ramcfg.data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt, - &ramcfg.size, &perfE); + &ramcfg.size, &perfE); if (!ramcfg.data || (ver < 0x25 || ver >= 0x40) || (ramcfg.size < 2)) { nv_error(pfb, "invalid/missing perftab entry\n"); @@ -103,7 +97,7 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) strap = nv_ro08(bios, ramcfg.data + 0x01); if (strap != 0xff) { timing.data = nvbios_timingEe(bios, strap, &ver, &hdr, - &cnt, &len); + &cnt, &len); if (!timing.data || ver != 0x10 || hdr < 0x12) { nv_error(pfb, "invalid/missing timing entry " "%02x %04x %02x %02x\n", @@ -136,7 +130,7 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) mpll.vco2.max_freq = 0; if (ret == 0) { ret = nv04_pll_calc(nv_subdev(pfb), &mpll, freq, - &N1, &M1, &N2, &M2, &P); + &N1, &M1, &N2, &M2, &P); if (ret == 0) ret = -EINVAL; } @@ -205,18 +199,18 @@ nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) } static int -nv50_ram_prog(struct nouveau_fb *pfb) +nv50_ram_prog(struct nvkm_fb *pfb) { - struct nouveau_device *device = nv_device(pfb); + struct nvkm_device *device = nv_device(pfb); struct nv50_ram *ram = (void *)pfb->ram; struct nv50_ramseq *hwsq = &ram->hwsq; - ram_exec(hwsq, nouveau_boolopt(device->cfgopt, "NvMemExec", true)); + ram_exec(hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); return 0; } static void -nv50_ram_tidy(struct nouveau_fb *pfb) +nv50_ram_tidy(struct nvkm_fb *pfb) { struct nv50_ram *ram = (void *)pfb->ram; struct nv50_ramseq *hwsq = &ram->hwsq; @@ -224,24 +218,24 @@ nv50_ram_tidy(struct nouveau_fb *pfb) } void -__nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem *mem) +__nv50_ram_put(struct nvkm_fb *pfb, struct nvkm_mem *mem) { - struct nouveau_mm_node *this; + struct nvkm_mm_node *this; while (!list_empty(&mem->regions)) { this = list_first_entry(&mem->regions, typeof(*this), rl_entry); list_del(&this->rl_entry); - nouveau_mm_free(&pfb->vram, &this); + nvkm_mm_free(&pfb->vram, &this); } - nouveau_mm_free(&pfb->tags, &mem->tag); + nvkm_mm_free(&pfb->tags, &mem->tag); } void -nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) +nv50_ram_put(struct nvkm_fb *pfb, struct nvkm_mem **pmem) { - struct nouveau_mem *mem = *pmem; + struct nvkm_mem *mem = *pmem; *pmem = NULL; if (unlikely(mem == NULL)) @@ -255,13 +249,13 @@ nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) } int -nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, - u32 memtype, struct nouveau_mem **pmem) +nv50_ram_get(struct nvkm_fb *pfb, u64 size, u32 align, u32 ncmin, + u32 memtype, struct nvkm_mem **pmem) { - struct nouveau_mm *heap = &pfb->vram; - struct nouveau_mm *tags = &pfb->tags; - struct nouveau_mm_node *r; - struct nouveau_mem *mem; + struct nvkm_mm *heap = &pfb->vram; + struct nvkm_mm *tags = &pfb->tags; + struct nvkm_mm_node *r; + struct nvkm_mem *mem; int comp = (memtype & 0x300) >> 8; int type = (memtype & 0x07f); int back = (memtype & 0x800); @@ -280,7 +274,7 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, if (align == 16) { int n = (max >> 4) * comp; - ret = nouveau_mm_head(tags, 0, 1, n, n, 1, &mem->tag); + ret = nvkm_mm_head(tags, 0, 1, n, n, 1, &mem->tag); if (ret) mem->tag = NULL; } @@ -296,9 +290,9 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, type = nv50_fb_memtype[type]; do { if (back) - ret = nouveau_mm_tail(heap, 0, type, max, min, align, &r); + ret = nvkm_mm_tail(heap, 0, type, max, min, align, &r); else - ret = nouveau_mm_head(heap, 0, type, max, min, align, &r); + ret = nvkm_mm_head(heap, 0, type, max, min, align, &r); if (ret) { mutex_unlock(&pfb->base.mutex); pfb->ram->put(pfb, &mem); @@ -310,14 +304,14 @@ nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, } while (max); mutex_unlock(&pfb->base.mutex); - r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry); + r = list_first_entry(&mem->regions, struct nvkm_mm_node, rl_entry); mem->offset = (u64)r->offset << 12; *pmem = mem; return 0; } static u32 -nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram) +nv50_fb_vram_rblock(struct nvkm_fb *pfb, struct nvkm_ram *ram) { int colbits, rowbitsa, rowbitsb, banks; u64 rowsize, predicted; @@ -326,8 +320,8 @@ nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram) r0 = nv_rd32(pfb, 0x100200); r4 = nv_rd32(pfb, 0x100204); rt = nv_rd32(pfb, 0x100250); - nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, - nv_rd32(pfb, 0x001540)); + nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", + r0, r4, rt, nv_rd32(pfb, 0x001540)); colbits = (r4 & 0x0000f000) >> 12; rowbitsa = ((r4 & 0x000f0000) >> 16) + 8; @@ -353,17 +347,17 @@ nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram) } int -nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, int length, void **pobject) +nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, int length, void **pobject) { const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ - struct nouveau_bios *bios = nouveau_bios(parent); - struct nouveau_fb *pfb = nouveau_fb(parent); - struct nouveau_ram *ram; + struct nvkm_bios *bios = nvkm_bios(parent); + struct nvkm_fb *pfb = nvkm_fb(parent); + struct nvkm_ram *ram; int ret; - ret = nouveau_ram_create_(parent, engine, oclass, length, pobject); + ret = nvkm_ram_create_(parent, engine, oclass, length, pobject); ram = *pobject; if (ret) return ret; @@ -377,7 +371,7 @@ nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, switch (nv_rd32(pfb, 0x100714) & 0x00000007) { case 0: ram->type = NV_MEM_TYPE_DDR1; break; case 1: - if (nouveau_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3) + if (nvkm_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3) ram->type = NV_MEM_TYPE_DDR3; else ram->type = NV_MEM_TYPE_DDR2; @@ -389,9 +383,9 @@ nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, break; } - ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) - - (rsvd_head + rsvd_tail), - nv50_fb_vram_rblock(pfb, ram) >> 12); + ret = nvkm_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) - + (rsvd_head + rsvd_tail), + nv50_fb_vram_rblock(pfb, ram) >> 12); if (ret) return ret; @@ -403,9 +397,9 @@ nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, } static int -nv50_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 datasize, - struct nouveau_object **pobject) +nv50_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 datasize, + struct nvkm_object **pobject) { struct nv50_ram *ram; int ret, i; @@ -459,12 +453,12 @@ nv50_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv50_ram_oclass = { - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_ram_ctor, - .dtor = _nouveau_ram_dtor, - .init = _nouveau_ram_init, - .fini = _nouveau_ram_fini, + .dtor = _nvkm_ram_dtor, + .init = _nvkm_ram_init, + .fini = _nvkm_ram_fini, } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h index 571077e..0f1f97c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h @@ -1,7 +1,5 @@ #ifndef __NVKM_FBRAM_SEQ_H__ #define __NVKM_FBRAM_SEQ_H__ - -#include <subdev/bus.h> #include <subdev/bus/hwsq.h> #define ram_init(s,p) hwsq_init(&(s)->base, (p)) @@ -14,5 +12,4 @@ #define ram_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) #define ram_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) #define ram_nsec(s,n) hwsq_nsec(&(s)->base, (n)) - #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h index 0f7fc0c..1f865f6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/regsnv04.h @@ -1,5 +1,5 @@ -#ifndef __NOUVEAU_FB_REGS_04_H__ -#define __NOUVEAU_FB_REGS_04_H__ +#ifndef __NVKM_FB_REGS_04_H__ +#define __NVKM_FB_REGS_04_H__ #define NV04_PFB_BOOT_0 0x00100000 # define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003 @@ -17,5 +17,6 @@ # define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028 # define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100 # define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000 +#define NV04_PFB_CFG0 0x00100200 #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c index 252575f..afab42d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c @@ -22,7 +22,6 @@ * Authors: Roy Spliet <rspliet@eclipso.eu> * Ben Skeggs */ - #include "priv.h" struct ramxlat { @@ -58,7 +57,7 @@ ramddr2_wr[] = { }; int -nouveau_sddr2_calc(struct nouveau_ram *ram) +nvkm_sddr2_calc(struct nvkm_ram *ram) { int CL, WR, DLL = 0, ODT = 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c index a2dca48..1084435 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c @@ -22,7 +22,6 @@ * Authors: Ben Skeggs <bskeggs@redhat.com> * Roy Spliet <rspliet@eclipso.eu> */ - #include "priv.h" struct ramxlat { @@ -67,7 +66,7 @@ ramddr3_cwl[] = { }; int -nouveau_sddr3_calc(struct nouveau_ram *ram) +nvkm_sddr3_calc(struct nvkm_ram *ram) { int CWL, CL, WR, DLL = 0, ODT = 0; |