diff options
Diffstat (limited to 'drivers/pci/host/pci-layerscape.c')
| -rw-r--r-- | drivers/pci/host/pci-layerscape.c | 38 |
1 files changed, 35 insertions, 3 deletions
diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c index 6537079..7ce32ff 100644 --- a/drivers/pci/host/pci-layerscape.c +++ b/drivers/pci/host/pci-layerscape.c @@ -35,12 +35,14 @@ #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ #define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */ -/* PEX LUT registers */ -#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */ +#define PCIE_IATU_NUM 6 + +static void ls_pcie_host_init(struct pcie_port *pp); struct ls_pcie_drvdata { u32 lut_offset; u32 ltssm_shift; + u32 lut_dbg; struct pcie_host_ops *ops; }; @@ -86,6 +88,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1); } +static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie) +{ + int i; + + for (i = 0; i < PCIE_IATU_NUM; i++) + dw_pcie_disable_outbound_atu(&pcie->pp, i); +} + static int ls1021_pcie_link_up(struct pcie_port *pp) { u32 state; @@ -134,7 +144,7 @@ static int ls_pcie_link_up(struct pcie_port *pp) struct ls_pcie *pcie = to_ls_pcie(pp); u32 state; - state = (ioread32(pcie->lut + PCIE_LUT_DBG) >> + state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> pcie->drvdata->ltssm_shift) & LTSSM_STATE_MASK; @@ -153,6 +163,9 @@ static void ls_pcie_host_init(struct pcie_port *pp) ls_pcie_clear_multifunction(pcie); ls_pcie_drop_msg_tlp(pcie); iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN); + + ls_pcie_disable_outbound_atus(pcie); + dw_pcie_setup_rc(pp); } static int ls_pcie_msi_host_init(struct pcie_port *pp, @@ -196,20 +209,39 @@ static struct ls_pcie_drvdata ls1021_drvdata = { static struct ls_pcie_drvdata ls1043_drvdata = { .lut_offset = 0x10000, .ltssm_shift = 24, + .lut_dbg = 0x7fc, + .ops = &ls_pcie_host_ops, +}; + +static struct ls_pcie_drvdata ls1046_drvdata = { + .lut_offset = 0x80000, + .ltssm_shift = 24, + .lut_dbg = 0x407fc, .ops = &ls_pcie_host_ops, }; static struct ls_pcie_drvdata ls2080_drvdata = { .lut_offset = 0x80000, .ltssm_shift = 0, + .lut_dbg = 0x7fc, + .ops = &ls_pcie_host_ops, +}; + +static struct ls_pcie_drvdata ls2088_drvdata = { + .lut_offset = 0x80000, + .ltssm_shift = 0, + .lut_dbg = 0x407fc, .ops = &ls_pcie_host_ops, }; static const struct of_device_id ls_pcie_of_match[] = { + { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata }, { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata }, { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata }, + { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata }, { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata }, + { .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata }, { }, }; |