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-rw-r--r--drivers/staging/et131x/et1310_eeprom.c8
-rw-r--r--drivers/staging/et131x/et1310_mac.c74
-rw-r--r--drivers/staging/et131x/et1310_phy.c70
-rw-r--r--drivers/staging/et131x/et1310_phy.h649
-rw-r--r--drivers/staging/et131x/et1310_pm.c34
-rw-r--r--drivers/staging/et131x/et1310_rx.c65
-rw-r--r--drivers/staging/et131x/et1310_tx.c4
-rw-r--r--drivers/staging/et131x/et131x.h4
-rw-r--r--drivers/staging/et131x/et131x_adapter.h63
-rw-r--r--drivers/staging/et131x/et131x_initpci.c50
-rw-r--r--drivers/staging/et131x/et131x_isr.c18
-rw-r--r--drivers/staging/et131x/et131x_netdev.c2
12 files changed, 364 insertions, 677 deletions
diff --git a/drivers/staging/et131x/et1310_eeprom.c b/drivers/staging/et131x/et1310_eeprom.c
index 5a8e6b9..2375840 100644
--- a/drivers/staging/et131x/et1310_eeprom.c
+++ b/drivers/staging/et131x/et1310_eeprom.c
@@ -396,12 +396,12 @@ int et131x_init_eeprom(struct et131x_adapter *etdev)
/* Read the EEPROM for information regarding LED behavior. Refer to
* ET1310_phy.c, et131x_xcvr_init(), for its use.
*/
- eeprom_read(etdev, 0x70, &etdev->eepromData[0]);
- eeprom_read(etdev, 0x71, &etdev->eepromData[1]);
+ eeprom_read(etdev, 0x70, &etdev->eeprom_data[0]);
+ eeprom_read(etdev, 0x71, &etdev->eeprom_data[1]);
- if (etdev->eepromData[0] != 0xcd)
+ if (etdev->eeprom_data[0] != 0xcd)
/* Disable all optional features */
- etdev->eepromData[1] = 0x00;
+ etdev->eeprom_data[1] = 0x00;
return 0;
}
diff --git a/drivers/staging/et131x/et1310_mac.c b/drivers/staging/et131x/et1310_mac.c
index 16fa13d..78f72fa 100644
--- a/drivers/staging/et131x/et1310_mac.c
+++ b/drivers/staging/et131x/et1310_mac.c
@@ -136,12 +136,12 @@ void ConfigMACRegs1(struct et131x_adapter *etdev)
* station address is used for generating and checking pause control
* packets.
*/
- station2.bits.Octet1 = etdev->CurrentAddress[0];
- station2.bits.Octet2 = etdev->CurrentAddress[1];
- station1.bits.Octet3 = etdev->CurrentAddress[2];
- station1.bits.Octet4 = etdev->CurrentAddress[3];
- station1.bits.Octet5 = etdev->CurrentAddress[4];
- station1.bits.Octet6 = etdev->CurrentAddress[5];
+ station2.bits.Octet1 = etdev->addr[0];
+ station2.bits.Octet2 = etdev->addr[1];
+ station1.bits.Octet3 = etdev->addr[2];
+ station1.bits.Octet4 = etdev->addr[3];
+ station1.bits.Octet5 = etdev->addr[4];
+ station1.bits.Octet6 = etdev->addr[5];
writel(station1.value, &pMac->station_addr_1.value);
writel(station2.value, &pMac->station_addr_2.value);
@@ -191,7 +191,7 @@ void ConfigMACRegs2(struct et131x_adapter *etdev)
cfg1 |= CFG1_RX_ENABLE|CFG1_TX_ENABLE|CFG1_TX_FLOW;
/* Initialize loop back to off */
cfg1 &= ~(CFG1_LOOPBACK|CFG1_RX_FLOW);
- if (etdev->FlowControl == RxOnly || etdev->FlowControl == Both)
+ if (etdev->flowcontrol == FLOW_RXONLY || etdev->flowcontrol == FLOW_BOTH)
cfg1 |= CFG1_RX_FLOW;
writel(cfg1, &pMac->cfg1);
@@ -280,14 +280,14 @@ void ConfigRxMacRegs(struct et131x_adapter *etdev)
writel(0, &pRxMac->mask4_word3);
/* Lets setup the WOL Source Address */
- sa_lo.bits.sa3 = etdev->CurrentAddress[2];
- sa_lo.bits.sa4 = etdev->CurrentAddress[3];
- sa_lo.bits.sa5 = etdev->CurrentAddress[4];
- sa_lo.bits.sa6 = etdev->CurrentAddress[5];
+ sa_lo.bits.sa3 = etdev->addr[2];
+ sa_lo.bits.sa4 = etdev->addr[3];
+ sa_lo.bits.sa5 = etdev->addr[4];
+ sa_lo.bits.sa6 = etdev->addr[5];
writel(sa_lo.value, &pRxMac->sa_lo.value);
- sa_hi.bits.sa1 = etdev->CurrentAddress[0];
- sa_hi.bits.sa2 = etdev->CurrentAddress[1];
+ sa_hi.bits.sa1 = etdev->addr[0];
+ sa_hi.bits.sa2 = etdev->addr[1];
writel(sa_hi.value, &pRxMac->sa_hi.value);
/* Disable all Packet Filtering */
@@ -373,7 +373,7 @@ void ConfigTxMacRegs(struct et131x_adapter *etdev)
* cfpt - control frame pause timer set to 64 (0x40)
* cfep - control frame extended pause timer set to 0x0
*/
- if (etdev->FlowControl == None)
+ if (etdev->flowcontrol == FLOW_NONE)
writel(0, &txmac->cf_param);
else
writel(0x40, &txmac->cf_param);
@@ -414,7 +414,7 @@ void ConfigMacStatRegs(struct et131x_adapter *etdev)
void ConfigFlowControl(struct et131x_adapter *etdev)
{
if (etdev->duplex_mode == 0) {
- etdev->FlowControl = None;
+ etdev->flowcontrol = FLOW_NONE;
} else {
char remote_pause, remote_async_pause;
@@ -426,22 +426,22 @@ void ConfigFlowControl(struct et131x_adapter *etdev)
if ((remote_pause == TRUEPHY_BIT_SET) &&
(remote_async_pause == TRUEPHY_BIT_SET)) {
- etdev->FlowControl = etdev->RegistryFlowControl;
+ etdev->flowcontrol = etdev->wanted_flow;
} else if ((remote_pause == TRUEPHY_BIT_SET) &&
(remote_async_pause == TRUEPHY_BIT_CLEAR)) {
- if (etdev->RegistryFlowControl == Both)
- etdev->FlowControl = Both;
+ if (etdev->wanted_flow == FLOW_BOTH)
+ etdev->flowcontrol = FLOW_BOTH;
else
- etdev->FlowControl = None;
+ etdev->flowcontrol = FLOW_NONE;
} else if ((remote_pause == TRUEPHY_BIT_CLEAR) &&
(remote_async_pause == TRUEPHY_BIT_CLEAR)) {
- etdev->FlowControl = None;
+ etdev->flowcontrol = FLOW_NONE;
} else {/* if (remote_pause == TRUEPHY_CLEAR_BIT &&
remote_async_pause == TRUEPHY_SET_BIT) */
- if (etdev->RegistryFlowControl == Both)
- etdev->FlowControl = RxOnly;
+ if (etdev->wanted_flow == FLOW_BOTH)
+ etdev->flowcontrol = FLOW_RXONLY;
else
- etdev->FlowControl = None;
+ etdev->flowcontrol = FLOW_NONE;
}
}
}
@@ -597,20 +597,20 @@ void SetupDeviceForUnicast(struct et131x_adapter *etdev)
* Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
* MAC address for first address
*/
- uni_pf3.bits.addr1_1 = etdev->CurrentAddress[0];
- uni_pf3.bits.addr1_2 = etdev->CurrentAddress[1];
- uni_pf3.bits.addr2_1 = etdev->CurrentAddress[0];
- uni_pf3.bits.addr2_2 = etdev->CurrentAddress[1];
-
- uni_pf2.bits.addr2_3 = etdev->CurrentAddress[2];
- uni_pf2.bits.addr2_4 = etdev->CurrentAddress[3];
- uni_pf2.bits.addr2_5 = etdev->CurrentAddress[4];
- uni_pf2.bits.addr2_6 = etdev->CurrentAddress[5];
-
- uni_pf1.bits.addr1_3 = etdev->CurrentAddress[2];
- uni_pf1.bits.addr1_4 = etdev->CurrentAddress[3];
- uni_pf1.bits.addr1_5 = etdev->CurrentAddress[4];
- uni_pf1.bits.addr1_6 = etdev->CurrentAddress[5];
+ uni_pf3.bits.addr1_1 = etdev->addr[0];
+ uni_pf3.bits.addr1_2 = etdev->addr[1];
+ uni_pf3.bits.addr2_1 = etdev->addr[0];
+ uni_pf3.bits.addr2_2 = etdev->addr[1];
+
+ uni_pf2.bits.addr2_3 = etdev->addr[2];
+ uni_pf2.bits.addr2_4 = etdev->addr[3];
+ uni_pf2.bits.addr2_5 = etdev->addr[4];
+ uni_pf2.bits.addr2_6 = etdev->addr[5];
+
+ uni_pf1.bits.addr1_3 = etdev->addr[2];
+ uni_pf1.bits.addr1_4 = etdev->addr[3];
+ uni_pf1.bits.addr1_5 = etdev->addr[4];
+ uni_pf1.bits.addr1_6 = etdev->addr[5];
pm_csr = readl(&etdev->regs->global.pm_csr);
if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
diff --git a/drivers/staging/et131x/et1310_phy.c b/drivers/staging/et131x/et1310_phy.c
index 21c5eee..2798a2f 100644
--- a/drivers/staging/et131x/et1310_phy.c
+++ b/drivers/staging/et131x/et1310_phy.c
@@ -242,23 +242,23 @@ int MiWrite(struct et131x_adapter *etdev, u8 xcvrReg, u16 value)
int et131x_xcvr_find(struct et131x_adapter *etdev)
{
u8 xcvr_addr;
- MI_IDR1_t idr1;
- MI_IDR2_t idr2;
+ u16 idr1;
+ u16 idr2;
u32 xcvr_id;
/* We need to get xcvr id and address we just get the first one */
for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
/* Read the ID from the PHY */
PhyMiRead(etdev, xcvr_addr,
- (u8) offsetof(MI_REGS_t, idr1),
- &idr1.value);
+ (u8) offsetof(struct mi_regs, idr1),
+ &idr1);
PhyMiRead(etdev, xcvr_addr,
- (u8) offsetof(MI_REGS_t, idr2),
- &idr2.value);
+ (u8) offsetof(struct mi_regs, idr2),
+ &idr2);
- xcvr_id = (u32) ((idr1.value << 16) | idr2.value);
+ xcvr_id = (u32) ((idr1 << 16) | idr2);
- if (idr1.value != 0 && idr1.value != 0xffff) {
+ if (idr1 != 0 && idr1 != 0xffff) {
etdev->Stats.xcvr_id = xcvr_id;
etdev->Stats.xcvr_addr = xcvr_addr;
return 0;
@@ -577,24 +577,22 @@ void et131x_setphy_normal(struct et131x_adapter *etdev)
*/
static void et131x_xcvr_init(struct et131x_adapter *etdev)
{
- MI_IMR_t imr;
- MI_ISR_t isr;
- MI_LCR2_t lcr2;
+ u16 imr;
+ u16 isr;
+ u16 lcr2;
/* Zero out the adapter structure variable representing BMSR */
etdev->Bmsr.value = 0;
- MiRead(etdev, (u8) offsetof(MI_REGS_t, isr), &isr.value);
- MiRead(etdev, (u8) offsetof(MI_REGS_t, imr), &imr.value);
+ MiRead(etdev, (u8) offsetof(struct mi_regs, isr), &isr);
+ MiRead(etdev, (u8) offsetof(struct mi_regs, imr), &imr);
/* Set the link status interrupt only. Bad behavior when link status
* and auto neg are set, we run into a nested interrupt problem
*/
- imr.bits.int_en = 0x1;
- imr.bits.link_status = 0x1;
- imr.bits.autoneg_status = 0x1;
+ imr |= 0x0105;
- MiWrite(etdev, (u8) offsetof(MI_REGS_t, imr), imr.value);
+ MiWrite(etdev, (u8) offsetof(struct mi_regs, imr), imr);
/* Set the LED behavior such that LED 1 indicates speed (off =
* 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
@@ -604,29 +602,33 @@ static void et131x_xcvr_init(struct et131x_adapter *etdev)
* vendors; The LED behavior is now determined by vendor data in the
* EEPROM. However, the above description is the default.
*/
- if ((etdev->eepromData[1] & 0x4) == 0) {
- MiRead(etdev, (u8) offsetof(MI_REGS_t, lcr2),
- &lcr2.value);
- if ((etdev->eepromData[1] & 0x8) == 0)
- lcr2.bits.led_tx_rx = 0x3;
+ if ((etdev->eeprom_data[1] & 0x4) == 0) {
+ MiRead(etdev, (u8) offsetof(struct mi_regs, lcr2),
+ &lcr2);
+
+ lcr2 &= 0x00FF;
+ lcr2 |= 0xA000; /* led link */
+
+ if ((etdev->eeprom_data[1] & 0x8) == 0)
+ lcr2 |= 0x0300;
else
- lcr2.bits.led_tx_rx = 0x4;
- lcr2.bits.led_link = 0xa;
- MiWrite(etdev, (u8) offsetof(MI_REGS_t, lcr2),
- lcr2.value);
+ lcr2 |= 0x0400;
+
+ MiWrite(etdev, (u8) offsetof(struct mi_regs, lcr2),
+ lcr2);
}
/* Determine if we need to go into a force mode and set it */
if (etdev->AiForceSpeed == 0 && etdev->AiForceDpx == 0) {
- if (etdev->RegistryFlowControl == TxOnly ||
- etdev->RegistryFlowControl == Both)
+ if (etdev->wanted_flow == FLOW_TXONLY ||
+ etdev->wanted_flow == FLOW_BOTH)
ET1310_PhyAccessMiBit(etdev,
TRUEPHY_BIT_SET, 4, 11, NULL);
else
ET1310_PhyAccessMiBit(etdev,
TRUEPHY_BIT_CLEAR, 4, 11, NULL);
- if (etdev->RegistryFlowControl == Both)
+ if (etdev->wanted_flow == FLOW_BOTH)
ET1310_PhyAccessMiBit(etdev,
TRUEPHY_BIT_SET, 4, 10, NULL);
else
@@ -645,15 +647,15 @@ static void et131x_xcvr_init(struct et131x_adapter *etdev)
/* Set to the correct force mode. */
if (etdev->AiForceDpx != 1) {
- if (etdev->RegistryFlowControl == TxOnly ||
- etdev->RegistryFlowControl == Both)
+ if (etdev->wanted_flow == FLOW_TXONLY ||
+ etdev->wanted_flow == FLOW_BOTH)
ET1310_PhyAccessMiBit(etdev,
TRUEPHY_BIT_SET, 4, 11, NULL);
else
ET1310_PhyAccessMiBit(etdev,
TRUEPHY_BIT_CLEAR, 4, 11, NULL);
- if (etdev->RegistryFlowControl == Both)
+ if (etdev->wanted_flow == FLOW_BOTH)
ET1310_PhyAccessMiBit(etdev,
TRUEPHY_BIT_SET, 4, 10, NULL);
else
@@ -740,7 +742,7 @@ void et131x_Mii_check(struct et131x_adapter *etdev,
if (bmsr_ints.bits.link_status) {
if (bmsr.bits.link_status) {
- etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
+ etdev->boot_coma = 20;
/* Update our state variables and indicate the
* connected state
@@ -831,7 +833,7 @@ void et131x_Mii_check(struct et131x_adapter *etdev,
etdev->linkspeed = speed;
etdev->duplex_mode = duplex;
- etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
+ etdev->boot_coma = 20;
if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
/*
diff --git a/drivers/staging/et131x/et1310_phy.h b/drivers/staging/et131x/et1310_phy.h
index 47907ba..78349ad 100644
--- a/drivers/staging/et131x/et1310_phy.h
+++ b/drivers/staging/et131x/et1310_phy.h
@@ -98,7 +98,7 @@
#define VMI_RESERVED31_REG 31
/* PHY Register Mapping(MI) Management Interface Regs */
-typedef struct _MI_REGS_t {
+struct mi_regs {
u8 bmcr; /* Basic mode control reg(Reg 0x00) */
u8 bmsr; /* Basic mode status reg(Reg 0x01) */
u8 idr1; /* Phy identifier reg 1(Reg 0x02) */
@@ -124,7 +124,7 @@ typedef struct _MI_REGS_t {
u8 lcr1; /* LED Control 1 Reg(Reg 0x1B) */
u8 lcr2; /* LED Control 2 Reg(Reg 0x1C) */
u8 mi_res4[3]; /* Future use by MI working group(Reg 0x1D - 0x1F) */
-} MI_REGS_t, *PMI_REGS_t;
+};
/* MI Register 0: Basic mode control register */
typedef union _MI_BMCR_t {
@@ -200,30 +200,6 @@ typedef union _MI_BMSR_t {
} bits;
} MI_BMSR_t, *PMI_BMSR_t;
-/* MI Register 2: Physical Identifier 1 */
-typedef union _MI_IDR1_t {
- u16 value;
- struct {
- u16 ieee_address:16; /* 0x0282 default(bits 0-15) */
- } bits;
-} MI_IDR1_t, *PMI_IDR1_t;
-
-/* MI Register 3: Physical Identifier 2 */
-typedef union _MI_IDR2_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 ieee_address:6; /* 111100 default(bits 10-15) */
- u16 model_no:6; /* 000001 default(bits 4-9) */
- u16 rev_no:4; /* 0010 default(bits 0-3) */
-#else
- u16 rev_no:4; /* 0010 default(bits 0-3) */
- u16 model_no:6; /* 000001 default(bits 4-9) */
- u16 ieee_address:6; /* 111100 default(bits 10-15) */
-#endif
- } bits;
-} MI_IDR2_t, *PMI_IDR2_t;
-
/* MI Register 4: Auto-negotiation advertisement register */
typedef union _MI_ANAR_t {
u16 value;
@@ -258,481 +234,194 @@ typedef union _MI_ANAR_t {
} bits;
} MI_ANAR_t, *PMI_ANAR_t;
-/* MI Register 5: Auto-negotiation link partner advertisement register */
-typedef struct _MI_ANLPAR_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 np_indication:1; /* bit 15 */
- u16 acknowledge:1; /* bit 14 */
- u16 remote_fault:1; /* bit 13 */
- u16 res1:1; /* bit 12 */
- u16 cap_asmpause:1; /* bit 11 */
- u16 cap_pause:1; /* bit 10 */
- u16 cap_100T4:1; /* bit 9 */
- u16 cap_100fdx:1; /* bit 8 */
- u16 cap_100hdx:1; /* bit 7 */
- u16 cap_10fdx:1; /* bit 6 */
- u16 cap_10hdx:1; /* bit 5 */
- u16 selector:5; /* bits 0-4 */
-#else
- u16 selector:5; /* bits 0-4 */
- u16 cap_10hdx:1; /* bit 5 */
- u16 cap_10fdx:1; /* bit 6 */
- u16 cap_100hdx:1; /* bit 7 */
- u16 cap_100fdx:1; /* bit 8 */
- u16 cap_100T4:1; /* bit 9 */
- u16 cap_pause:1; /* bit 10 */
- u16 cap_asmpause:1; /* bit 11 */
- u16 res1:1; /* bit 12 */
- u16 remote_fault:1; /* bit 13 */
- u16 acknowledge:1; /* bit 14 */
- u16 np_indication:1; /* bit 15 */
-#endif
- } bits;
-} MI_ANLPAR_t, *PMI_ANLPAR_t;
+/* MI Register 5: Auto-negotiation link partner advertisement register
+ * 15: np_indication
+ * 14: acknowledge
+ * 13: remote_fault
+ * 12: res1:1;
+ * 11: cap_asmpause
+ * 10: cap_pause
+ * 9: cap_100T4
+ * 8: cap_100fdx
+ * 7: cap_100hdx
+ * 6: cap_10fdx
+ * 5: cap_10hdx
+ * 4-0: selector
+ */
-/* MI Register 6: Auto-negotiation expansion register */
-typedef union _MI_ANER_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 res:11; /* bits 5-15 */
- u16 pdf:1; /* bit 4 */
- u16 lp_np_able:1; /* bit 3 */
- u16 np_able:1; /* bit 2 */
- u16 page_rx:1; /* bit 1 */
- u16 lp_an_able:1; /* bit 0 */
-#else
- u16 lp_an_able:1; /* bit 0 */
- u16 page_rx:1; /* bit 1 */
- u16 np_able:1; /* bit 2 */
- u16 lp_np_able:1; /* bit 3 */
- u16 pdf:1; /* bit 4 */
- u16 res:11; /* bits 5-15 */
-#endif
- } bits;
-} MI_ANER_t, *PMI_ANER_t;
+/* MI Register 6: Auto-negotiation expansion register
+ * 15-5: reserved
+ * 4: pdf
+ * 3: lp_np_able
+ * 2: np_able
+ * 1: page_rx
+ * 0: lp_an_able
+ */
-/* MI Register 7: Auto-negotiation next page transmit reg(0x07) */
-typedef union _MI_ANNPTR_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 np:1; /* bit 15 */
- u16 res1:1; /* bit 14 */
- u16 msg_page:1; /* bit 13 */
- u16 ack2:1; /* bit 12 */
- u16 toggle:1; /* bit 11 */
- u16 msg:11; /* bits 0-10 */
-#else
- u16 msg:11; /* bits 0-10 */
- u16 toggle:1; /* bit 11 */
- u16 ack2:1; /* bit 12 */
- u16 msg_page:1; /* bit 13 */
- u16 res1:1; /* bit 14 */
- u16 np:1; /* bit 15 */
-#endif
- } bits;
-} MI_ANNPTR_t, *PMI_ANNPTR_t;
+/* MI Register 7: Auto-negotiation next page transmit reg(0x07)
+ * 15: np
+ * 14: reserved
+ * 13: msg_page
+ * 12: ack2
+ * 11: toggle
+ * 10-0 msg
+ */
-/* MI Register 8: Link Partner Next Page Reg(0x08) */
-typedef union _MI_LPNPR_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 np:1; /* bit 15 */
- u16 ack:1; /* bit 14 */
- u16 msg_page:1; /* bit 13 */
- u16 ack2:1; /* bit 12 */
- u16 toggle:1; /* bit 11 */
- u16 msg:11; /* bits 0-10 */
-#else
- u16 msg:11; /* bits 0-10 */
- u16 toggle:1; /* bit 11 */
- u16 ack2:1; /* bit 12 */
- u16 msg_page:1; /* bit 13 */
- u16 ack:1; /* bit 14 */
- u16 np:1; /* bit 15 */
-#endif
- } bits;
-} MI_LPNPR_t, *PMI_LPNPR_t;
+/* MI Register 8: Link Partner Next Page Reg(0x08)
+ * 15: np
+ * 14: ack
+ * 13: msg_page
+ * 12: ack2
+ * 11: toggle
+ * 10-0: msg
+ */
-/* MI Register 9: 1000BaseT Control Reg(0x09) */
-typedef union _MI_GCR_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 test_mode:3; /* bits 13-15 */
- u16 ms_config_en:1; /* bit 12 */
- u16 ms_value:1; /* bit 11 */
- u16 port_type:1; /* bit 10 */
- u16 link_1000fdx:1; /* bit 9 */
- u16 link_1000hdx:1; /* bit 8 */
- u16 res:8; /* bit 0-7 */
-#else
- u16 res:8; /* bit 0-7 */
- u16 link_1000hdx:1; /* bit 8 */
- u16 link_1000fdx:1; /* bit 9 */
- u16 port_type:1; /* bit 10 */
- u16 ms_value:1; /* bit 11 */
- u16 ms_config_en:1; /* bit 12 */
- u16 test_mode:3; /* bits 13-15 */
-#endif
- } bits;
-} MI_GCR_t, *PMI_GCR_t;
+/* MI Register 9: 1000BaseT Control Reg(0x09)
+ * 15-13: test_mode
+ * 12: ms_config_en
+ * 11: ms_value
+ * 10: port_type
+ * 9: link_1000fdx
+ * 8: link_1000hdx
+ * 7-0: reserved
+ */
-/* MI Register 10: 1000BaseT Status Reg(0x0A) */
-typedef union _MI_GSR_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 ms_config_fault:1; /* bit 15 */
- u16 ms_resolve:1; /* bit 14 */
- u16 local_rx_status:1; /* bit 13 */
- u16 remote_rx_status:1; /* bit 12 */
- u16 link_1000fdx:1; /* bit 11 */
- u16 link_1000hdx:1; /* bit 10 */
- u16 res:2; /* bits 8-9 */
- u16 idle_err_cnt:8; /* bits 0-7 */
-#else
- u16 idle_err_cnt:8; /* bits 0-7 */
- u16 res:2; /* bits 8-9 */
- u16 link_1000hdx:1; /* bit 10 */
- u16 link_1000fdx:1; /* bit 11 */
- u16 remote_rx_status:1; /* bit 12 */
- u16 local_rx_status:1; /* bit 13 */
- u16 ms_resolve:1; /* bit 14 */
- u16 ms_config_fault:1; /* bit 15 */
-#endif
- } bits;
-} MI_GSR_t, *PMI_GSR_t;
+/* MI Register 10: 1000BaseT Status Reg(0x0A)
+ * 15: ms_config_fault
+ * 14: ms_resolve
+ * 13: local_rx_status
+ * 12: remote_rx_status
+ * 11: link_1000fdx
+ * 10: link_1000hdx
+ * 9-8: reserved
+ * 7-0: idle_err_cnt
+ */
/* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */
-typedef union _MI_RES_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 res15:1; /* bit 15 */
- u16 res14:1; /* bit 14 */
- u16 res13:1; /* bit 13 */
- u16 res12:1; /* bit 12 */
- u16 res11:1; /* bit 11 */
- u16 res10:1; /* bit 10 */
- u16 res9:1; /* bit 9 */
- u16 res8:1; /* bit 8 */
- u16 res7:1; /* bit 7 */
- u16 res6:1; /* bit 6 */
- u16 res5:1; /* bit 5 */
- u16 res4:1; /* bit 4 */
- u16 res3:1; /* bit 3 */
- u16 res2:1; /* bit 2 */
- u16 res1:1; /* bit 1 */
- u16 res0:1; /* bit 0 */
-#else
- u16 res0:1; /* bit 0 */
- u16 res1:1; /* bit 1 */
- u16 res2:1; /* bit 2 */
- u16 res3:1; /* bit 3 */
- u16 res4:1; /* bit 4 */
- u16 res5:1; /* bit 5 */
- u16 res6:1; /* bit 6 */
- u16 res7:1; /* bit 7 */
- u16 res8:1; /* bit 8 */
- u16 res9:1; /* bit 9 */
- u16 res10:1; /* bit 10 */
- u16 res11:1; /* bit 11 */
- u16 res12:1; /* bit 12 */
- u16 res13:1; /* bit 13 */
- u16 res14:1; /* bit 14 */
- u16 res15:1; /* bit 15 */
-#endif
- } bits;
-} MI_RES_t, *PMI_RES_t;
-/* MI Register 15: Extended status Reg(0x0F) */
-typedef union _MI_ESR_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 link_1000Xfdx:1; /* bit 15 */
- u16 link_1000Xhdx:1; /* bit 14 */
- u16 link_1000fdx:1; /* bit 13 */
- u16 link_1000hdx:1; /* bit 12 */
- u16 res:12; /* bit 0-11 */
-#else
- u16 res:12; /* bit 0-11 */
- u16 link_1000hdx:1; /* bit 12 */
- u16 link_1000fdx:1; /* bit 13 */
- u16 link_1000Xhdx:1; /* bit 14 */
- u16 link_1000Xfdx:1; /* bit 15 */
-#endif
- } bits;
-} MI_ESR_t, *PMI_ESR_t;
+/* MI Register 15: Extended status Reg(0x0F)
+ * 15: link_1000Xfdx
+ * 14: link_1000Xhdx
+ * 13: link_1000fdx
+ * 12: link_1000hdx
+ * 11-0: reserved
+ */
/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
-/* MI Register 19: Loopback Control Reg(0x13) */
-typedef union _MI_LCR_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 mii_en:1; /* bit 15 */
- u16 pcs_en:1; /* bit 14 */
- u16 pmd_en:1; /* bit 13 */
- u16 all_digital_en:1; /* bit 12 */
- u16 replica_en:1; /* bit 11 */
- u16 line_driver_en:1; /* bit 10 */
- u16 res:10; /* bit 0-9 */
-#else
- u16 res:10; /* bit 0-9 */
- u16 line_driver_en:1; /* bit 10 */
- u16 replica_en:1; /* bit 11 */
- u16 all_digital_en:1; /* bit 12 */
- u16 pmd_en:1; /* bit 13 */
- u16 pcs_en:1; /* bit 14 */
- u16 mii_en:1; /* bit 15 */
-#endif
- } bits;
-} MI_LCR_t, *PMI_LCR_t;
+/* MI Register 19: Loopback Control Reg(0x13)
+ * 15: mii_en
+ * 14: pcs_en
+ * 13: pmd_en
+ * 12: all_digital_en
+ * 11: replica_en
+ * 10: line_driver_en
+ * 9-0: reserved
+ */
/* MI Register 20: Reserved Reg(0x14) */
-/* MI Register 21: Management Interface Control Reg(0x15) */
-typedef union _MI_MICR_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 res1:5; /* bits 11-15 */
- u16 mi_error_count:7; /* bits 4-10 */
- u16 res2:1; /* bit 3 */
- u16 ignore_10g_fr:1; /* bit 2 */
- u16 res3:1; /* bit 1 */
- u16 preamble_supress_en:1; /* bit 0 */
-#else
- u16 preamble_supress_en:1; /* bit 0 */
- u16 res3:1; /* bit 1 */
- u16 ignore_10g_fr:1; /* bit 2 */
- u16 res2:1; /* bit 3 */
- u16 mi_error_count:7; /* bits 4-10 */
- u16 res1:5; /* bits 11-15 */
-#endif
- } bits;
-} MI_MICR_t, *PMI_MICR_t;
+/* MI Register 21: Management Interface Control Reg(0x15)
+ * 15-11: reserved
+ * 10-4: mi_error_count
+ * 3: reserved
+ * 2: ignore_10g_fr
+ * 1: reserved
+ * 0: preamble_supress_en
+ */
-/* MI Register 22: PHY Configuration Reg(0x16) */
-typedef union _MI_PHY_CONFIG_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 crs_tx_en:1; /* bit 15 */
- u16 res1:1; /* bit 14 */
- u16 tx_fifo_depth:2; /* bits 12-13 */
- u16 speed_downshift:2; /* bits 10-11 */
- u16 pbi_detect:1; /* bit 9 */
- u16 tbi_rate:1; /* bit 8 */
- u16 alternate_np:1; /* bit 7 */
- u16 group_mdio_en:1; /* bit 6 */
- u16 tx_clock_en:1; /* bit 5 */
- u16 sys_clock_en:1; /* bit 4 */
- u16 res2:1; /* bit 3 */
- u16 mac_if_mode:3; /* bits 0-2 */
-#else
- u16 mac_if_mode:3; /* bits 0-2 */
- u16 res2:1; /* bit 3 */
- u16 sys_clock_en:1; /* bit 4 */
- u16 tx_clock_en:1; /* bit 5 */
- u16 group_mdio_en:1; /* bit 6 */
- u16 alternate_np:1; /* bit 7 */
- u16 tbi_rate:1; /* bit 8 */
- u16 pbi_detect:1; /* bit 9 */
- u16 speed_downshift:2; /* bits 10-11 */
- u16 tx_fifo_depth:2; /* bits 12-13 */
- u16 res1:1; /* bit 14 */
- u16 crs_tx_en:1; /* bit 15 */
-#endif
- } bits;
-} MI_PHY_CONFIG_t, *PMI_PHY_CONFIG_t;
+/* MI Register 22: PHY Configuration Reg(0x16)
+ * 15: crs_tx_en
+ * 14: reserved
+ * 13-12: tx_fifo_depth
+ * 11-10: speed_downshift
+ * 9: pbi_detect
+ * 8: tbi_rate
+ * 7: alternate_np
+ * 6: group_mdio_en
+ * 5: tx_clock_en
+ * 4: sys_clock_en
+ * 3: reserved
+ * 2-0: mac_if_mode
+ */
-/* MI Register 23: PHY CONTROL Reg(0x17) */
-typedef union _MI_PHY_CONTROL_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 res1:1; /* bit 15 */
- u16 tdr_en:1; /* bit 14 */
- u16 res2:1; /* bit 13 */
- u16 downshift_attempts:2; /* bits 11-12 */
- u16 res3:5; /* bit 6-10 */
- u16 jabber_10baseT:1; /* bit 5 */
- u16 sqe_10baseT:1; /* bit 4 */
- u16 tp_loopback_10baseT:1; /* bit 3 */
- u16 preamble_gen_en:1; /* bit 2 */
- u16 res4:1; /* bit 1 */
- u16 force_int:1; /* bit 0 */
-#else
- u16 force_int:1; /* bit 0 */
- u16 res4:1; /* bit 1 */
- u16 preamble_gen_en:1; /* bit 2 */
- u16 tp_loopback_10baseT:1; /* bit 3 */
- u16 sqe_10baseT:1; /* bit 4 */
- u16 jabber_10baseT:1; /* bit 5 */
- u16 res3:5; /* bit 6-10 */
- u16 downshift_attempts:2; /* bits 11-12 */
- u16 res2:1; /* bit 13 */
- u16 tdr_en:1; /* bit 14 */
- u16 res1:1; /* bit 15 */
-#endif
- } bits;
-} MI_PHY_CONTROL_t, *PMI_PHY_CONTROL_t;
+/* MI Register 23: PHY CONTROL Reg(0x17)
+ * 15: reserved
+ * 14: tdr_en
+ * 13: reserved
+ * 12-11: downshift_attempts
+ * 10-6: reserved
+ * 5: jabber_10baseT
+ * 4: sqe_10baseT
+ * 3: tp_loopback_10baseT
+ * 2: preamble_gen_en
+ * 1: reserved
+ * 0: force_int
+ */
-/* MI Register 24: Interrupt Mask Reg(0x18) */
-typedef union _MI_IMR_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 res1:6; /* bits 10-15 */
- u16 mdio_sync_lost:1; /* bit 9 */
- u16 autoneg_status:1; /* bit 8 */
- u16 hi_bit_err:1; /* bit 7 */
- u16 np_rx:1; /* bit 6 */
- u16 err_counter_full:1; /* bit 5 */
- u16 fifo_over_underflow:1; /* bit 4 */
- u16 rx_status:1; /* bit 3 */
- u16 link_status:1; /* bit 2 */
- u16 automatic_speed:1; /* bit 1 */
- u16 int_en:1; /* bit 0 */
-#else
- u16 int_en:1; /* bit 0 */
- u16 automatic_speed:1; /* bit 1 */
- u16 link_status:1; /* bit 2 */
- u16 rx_status:1; /* bit 3 */
- u16 fifo_over_underflow:1; /* bit 4 */
- u16 err_counter_full:1; /* bit 5 */
- u16 np_rx:1; /* bit 6 */
- u16 hi_bit_err:1; /* bit 7 */
- u16 autoneg_status:1; /* bit 8 */
- u16 mdio_sync_lost:1; /* bit 9 */
- u16 res1:6; /* bits 10-15 */
-#endif
- } bits;
-} MI_IMR_t, *PMI_IMR_t;
+/* MI Register 24: Interrupt Mask Reg(0x18)
+ * 15-10: reserved
+ * 9: mdio_sync_lost
+ * 8: autoneg_status
+ * 7: hi_bit_err
+ * 6: np_rx
+ * 5: err_counter_full
+ * 4: fifo_over_underflow
+ * 3: rx_status
+ * 2: link_status
+ * 1: automatic_speed
+ * 0: int_en
+ */
-/* MI Register 25: Interrupt Status Reg(0x19) */
-typedef union _MI_ISR_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 res1:6; /* bits 10-15 */
- u16 mdio_sync_lost:1; /* bit 9 */
- u16 autoneg_status:1; /* bit 8 */
- u16 hi_bit_err:1; /* bit 7 */
- u16 np_rx:1; /* bit 6 */
- u16 err_counter_full:1; /* bit 5 */
- u16 fifo_over_underflow:1; /* bit 4 */
- u16 rx_status:1; /* bit 3 */
- u16 link_status:1; /* bit 2 */
- u16 automatic_speed:1; /* bit 1 */
- u16 int_en:1; /* bit 0 */
-#else
- u16 int_en:1; /* bit 0 */
- u16 automatic_speed:1; /* bit 1 */
- u16 link_status:1; /* bit 2 */
- u16 rx_status:1; /* bit 3 */
- u16 fifo_over_underflow:1; /* bit 4 */
- u16 err_counter_full:1; /* bit 5 */
- u16 np_rx:1; /* bit 6 */
- u16 hi_bit_err:1; /* bit 7 */
- u16 autoneg_status:1; /* bit 8 */
- u16 mdio_sync_lost:1; /* bit 9 */
- u16 res1:6; /* bits 10-15 */
-#endif
- } bits;
-} MI_ISR_t, *PMI_ISR_t;
-/* MI Register 26: PHY Status Reg(0x1A) */
-typedef union _MI_PSR_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 res1:1; /* bit 15 */
- u16 autoneg_fault:2; /* bit 13-14 */
- u16 autoneg_status:1; /* bit 12 */
- u16 mdi_x_status:1; /* bit 11 */
- u16 polarity_status:1; /* bit 10 */
- u16 speed_status:2; /* bits 8-9 */
- u16 duplex_status:1; /* bit 7 */
- u16 link_status:1; /* bit 6 */
- u16 tx_status:1; /* bit 5 */
- u16 rx_status:1; /* bit 4 */
- u16 collision_status:1; /* bit 3 */
- u16 autoneg_en:1; /* bit 2 */
- u16 pause_en:1; /* bit 1 */
- u16 asymmetric_dir:1; /* bit 0 */
-#else
- u16 asymmetric_dir:1; /* bit 0 */
- u16 pause_en:1; /* bit 1 */
- u16 autoneg_en:1; /* bit 2 */
- u16 collision_status:1; /* bit 3 */
- u16 rx_status:1; /* bit 4 */
- u16 tx_status:1; /* bit 5 */
- u16 link_status:1; /* bit 6 */
- u16 duplex_status:1; /* bit 7 */
- u16 speed_status:2; /* bits 8-9 */
- u16 polarity_status:1; /* bit 10 */
- u16 mdi_x_status:1; /* bit 11 */
- u16 autoneg_status:1; /* bit 12 */
- u16 autoneg_fault:2; /* bit 13-14 */
- u16 res1:1; /* bit 15 */
-#endif
- } bits;
-} MI_PSR_t, *PMI_PSR_t;
+/* MI Register 25: Interrupt Status Reg(0x19)
+ * 15-10: reserved
+ * 9: mdio_sync_lost
+ * 8: autoneg_status
+ * 7: hi_bit_err
+ * 6: np_rx
+ * 5: err_counter_full
+ * 4: fifo_over_underflow
+ * 3: rx_status
+ * 2: link_status
+ * 1: automatic_speed
+ * 0: int_en
+ */
-/* MI Register 27: LED Control Reg 1(0x1B) */
-typedef union _MI_LCR1_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 res1:2; /* bits 14-15 */
- u16 led_dup_indicate:2; /* bits 12-13 */
- u16 led_10baseT:2; /* bits 10-11 */
- u16 led_collision:2; /* bits 8-9 */
- u16 res2:2; /* bits 6-7 */
- u16 res3:2; /* bits 4-5 */
- u16 pulse_dur:2; /* bits 2-3 */
- u16 pulse_stretch1:1; /* bit 1 */
- u16 pulse_stretch0:1; /* bit 0 */
-#else
- u16 pulse_stretch0:1; /* bit 0 */
- u16 pulse_stretch1:1; /* bit 1 */
- u16 pulse_dur:2; /* bits 2-3 */
- u16 res3:2; /* bits 4-5 */
- u16 res2:2; /* bits 6-7 */
- u16 led_collision:2; /* bits 8-9 */
- u16 led_10baseT:2; /* bits 10-11 */
- u16 led_dup_indicate:2; /* bits 12-13 */
- u16 res1:2; /* bits 14-15 */
-#endif
- } bits;
-} MI_LCR1_t, *PMI_LCR1_t;
+/* MI Register 26: PHY Status Reg(0x1A)
+ * 15: reserved
+ * 14-13: autoneg_fault
+ * 12: autoneg_status
+ * 11: mdi_x_status
+ * 10: polarity_status
+ * 9-8: speed_status
+ * 7: duplex_status
+ * 6: link_status
+ * 5: tx_status
+ * 4: rx_status
+ * 3: collision_status
+ * 2: autoneg_en
+ * 1: pause_en
+ * 0: asymmetric_dir
+ */
-/* MI Register 28: LED Control Reg 2(0x1C) */
-typedef union _MI_LCR2_t {
- u16 value;
- struct {
-#ifdef _BIT_FIELDS_HTOL
- u16 led_link:4; /* bits 12-15 */
- u16 led_tx_rx:4; /* bits 8-11 */
- u16 led_100BaseTX:4; /* bits 4-7 */
- u16 led_1000BaseT:4; /* bits 0-3 */
-#else
- u16 led_1000BaseT:4; /* bits 0-3 */
- u16 led_100BaseTX:4; /* bits 4-7 */
- u16 led_tx_rx:4; /* bits 8-11 */
- u16 led_link:4; /* bits 12-15 */
-#endif
- } bits;
-} MI_LCR2_t, *PMI_LCR2_t;
+/* MI Register 27: LED Control Reg 1(0x1B)
+ * 15-14: reserved
+ * 13-12: led_dup_indicate
+ * 11-10: led_10baseT
+ * 9-8: led_collision
+ * 7-4: reserved
+ * 3-2: pulse_dur
+ * 1: pulse_stretch1
+ * 0: pulse_stretch0
+ */
+
+/* MI Register 28: LED Control Reg 2(0x1C)
+ * 15-12: led_link
+ * 11-8: led_tx_rx
+ * 7-4: led_100BaseTX
+ * 3-0: led_1000BaseT
+ */
/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
diff --git a/drivers/staging/et131x/et1310_pm.c b/drivers/staging/et131x/et1310_pm.c
index c64bb2c..2bc1944 100644
--- a/drivers/staging/et131x/et1310_pm.c
+++ b/drivers/staging/et131x/et1310_pm.c
@@ -109,30 +109,30 @@
void EnablePhyComa(struct et131x_adapter *etdev)
{
unsigned long flags;
- u32 GlobalPmCSR;
+ u32 pmcsr;
- GlobalPmCSR = readl(&etdev->regs->global.pm_csr);
+ pmcsr = readl(&etdev->regs->global.pm_csr);
/* Save the GbE PHY speed and duplex modes. Need to restore this
* when cable is plugged back in
*/
- etdev->PoMgmt.PowerDownSpeed = etdev->AiForceSpeed;
- etdev->PoMgmt.PowerDownDuplex = etdev->AiForceDpx;
+ etdev->pdown_speed = etdev->AiForceSpeed;
+ etdev->pdown_duplex = etdev->AiForceDpx;
/* Stop sending packets. */
- spin_lock_irqsave(&etdev->SendHWLock, flags);
+ spin_lock_irqsave(&etdev->send_hw_lock, flags);
etdev->Flags |= fMP_ADAPTER_LOWER_POWER;
- spin_unlock_irqrestore(&etdev->SendHWLock, flags);
+ spin_unlock_irqrestore(&etdev->send_hw_lock, flags);
/* Wait for outstanding Receive packets */
/* Gate off JAGCore 3 clock domains */
- GlobalPmCSR &= ~ET_PMCSR_INIT;
- writel(GlobalPmCSR, &etdev->regs->global.pm_csr);
+ pmcsr &= ~ET_PMCSR_INIT;
+ writel(pmcsr, &etdev->regs->global.pm_csr);
/* Program gigE PHY in to Coma mode */
- GlobalPmCSR |= ET_PM_PHY_SW_COMA;
- writel(GlobalPmCSR, &etdev->regs->global.pm_csr);
+ pmcsr |= ET_PM_PHY_SW_COMA;
+ writel(pmcsr, &etdev->regs->global.pm_csr);
}
/**
@@ -141,20 +141,20 @@ void EnablePhyComa(struct et131x_adapter *etdev)
*/
void DisablePhyComa(struct et131x_adapter *etdev)
{
- u32 GlobalPmCSR;
+ u32 pmcsr;
- GlobalPmCSR = readl(&etdev->regs->global.pm_csr);
+ pmcsr = readl(&etdev->regs->global.pm_csr);
/* Disable phy_sw_coma register and re-enable JAGCore clocks */
- GlobalPmCSR |= ET_PMCSR_INIT;
- GlobalPmCSR &= ~ET_PM_PHY_SW_COMA;
- writel(GlobalPmCSR, &etdev->regs->global.pm_csr);
+ pmcsr |= ET_PMCSR_INIT;
+ pmcsr &= ~ET_PM_PHY_SW_COMA;
+ writel(pmcsr, &etdev->regs->global.pm_csr);
/* Restore the GbE PHY speed and duplex modes;
* Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
*/
- etdev->AiForceSpeed = etdev->PoMgmt.PowerDownSpeed;
- etdev->AiForceDpx = etdev->PoMgmt.PowerDownDuplex;
+ etdev->AiForceSpeed = etdev->pdown_speed;
+ etdev->AiForceDpx = etdev->pdown_duplex;
/* Re-initialize the send structures */
et131x_init_send(etdev);
diff --git a/drivers/staging/et131x/et1310_rx.c b/drivers/staging/et131x/et1310_rx.c
index 8e04bdd..339136f 100644
--- a/drivers/staging/et131x/et1310_rx.c
+++ b/drivers/staging/et131x/et1310_rx.c
@@ -88,7 +88,7 @@
#include "et1310_rx.h"
#include "et131x.h"
-void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd);
+void nic_return_rfd(struct et131x_adapter *etdev, struct rfd *rfd);
/**
* et131x_rx_dma_memory_alloc
@@ -372,7 +372,7 @@ int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
* RFDs will be allocated from this pool.
*/
rx_ring->RecvLookaside = kmem_cache_create(adapter->netdev->name,
- sizeof(MP_RFD),
+ sizeof(struct rfd),
0,
SLAB_CACHE_DMA |
SLAB_HWCACHE_ALIGN,
@@ -396,7 +396,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
u32 index;
u32 bufsize;
u32 pktStatRingSize;
- PMP_RFD rfd;
+ struct rfd *rfd;
struct rx_ring *rx_ring;
/* Setup some convenience pointers */
@@ -406,11 +406,11 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
WARN_ON(rx_ring->nReadyRecv != rx_ring->NumRfd);
while (!list_empty(&rx_ring->RecvList)) {
- rfd = (MP_RFD *) list_entry(rx_ring->RecvList.next,
- MP_RFD, list_node);
+ rfd = (struct rfd *) list_entry(rx_ring->RecvList.next,
+ struct rfd, list_node);
list_del(&rfd->list_node);
- rfd->Packet = NULL;
+ rfd->skb = NULL;
kmem_cache_free(adapter->rx_ring.RecvLookaside, rfd);
}
@@ -537,7 +537,7 @@ void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
int et131x_init_recv(struct et131x_adapter *adapter)
{
int status = -ENOMEM;
- PMP_RFD rfd = NULL;
+ struct rfd *rfd = NULL;
u32 rfdct;
u32 numrfd = 0;
struct rx_ring *rx_ring;
@@ -557,7 +557,7 @@ int et131x_init_recv(struct et131x_adapter *adapter)
continue;
}
- rfd->Packet = NULL;
+ rfd->skb = NULL;
/* Add this RFD to the RecvList */
list_add_tail(&rfd->list_node, &rx_ring->RecvList);
@@ -622,7 +622,7 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev)
writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
&rx_dma->psr_min_des);
- spin_lock_irqsave(&etdev->RcvLock, flags);
+ spin_lock_irqsave(&etdev->rcv_lock, flags);
/* These local variables track the PSR in the adapter structure */
rx_local->local_psr_full = 0;
@@ -688,7 +688,7 @@ void ConfigRxDmaRegs(struct et131x_adapter *etdev)
*/
writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
- spin_unlock_irqrestore(&etdev->RcvLock, flags);
+ spin_unlock_irqrestore(&etdev->rcv_lock, flags);
}
/**
@@ -717,10 +717,10 @@ void et131x_rx_dma_disable(struct et131x_adapter *etdev)
/* Setup the receive dma configuration register */
writel(0x00002001, &etdev->regs->rxdma.csr);
csr = readl(&etdev->regs->rxdma.csr);
- if ((csr & 0x00020000) != 1) { /* Check halt status (bit 17) */
+ if ((csr & 0x00020000) == 0) { /* Check halt status (bit 17) */
udelay(5);
csr = readl(&etdev->regs->rxdma.csr);
- if ((csr & 0x00020000) != 1)
+ if ((csr & 0x00020000) == 0)
dev_err(&etdev->pdev->dev,
"RX Dma failed to enter halt state. CSR 0x%08x\n",
csr);
@@ -776,12 +776,12 @@ void et131x_rx_dma_enable(struct et131x_adapter *etdev)
* the packet to it, puts the RFD in the RecvPendList, and also returns
* the pointer to the RFD.
*/
-PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
+struct rfd * nic_rx_pkts(struct et131x_adapter *etdev)
{
struct rx_ring *rx_local = &etdev->rx_ring;
struct rx_status_block *status;
struct pkt_stat_desc *psr;
- PMP_RFD rfd;
+ struct rfd *rfd;
u32 i;
u8 *buf;
unsigned long flags;
@@ -854,21 +854,21 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
}
/* Get and fill the RFD. */
- spin_lock_irqsave(&etdev->RcvLock, flags);
+ spin_lock_irqsave(&etdev->rcv_lock, flags);
rfd = NULL;
element = rx_local->RecvList.next;
- rfd = (PMP_RFD) list_entry(element, MP_RFD, list_node);
+ rfd = (struct rfd *) list_entry(element, struct rfd, list_node);
if (rfd == NULL) {
- spin_unlock_irqrestore(&etdev->RcvLock, flags);
+ spin_unlock_irqrestore(&etdev->rcv_lock, flags);
return NULL;
}
list_del(&rfd->list_node);
rx_local->nReadyRecv--;
- spin_unlock_irqrestore(&etdev->RcvLock, flags);
+ spin_unlock_irqrestore(&etdev->rcv_lock, flags);
rfd->bufferindex = bindex;
rfd->ringindex = rindex;
@@ -887,8 +887,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
if (etdev->ReplicaPhyLoopbk == 1) {
buf = rx_local->fbr[rindex]->virt[bindex];
- if (memcmp(&buf[6], &etdev->CurrentAddress[0],
- ETH_ALEN) == 0) {
+ if (memcmp(&buf[6], etdev->addr, ETH_ALEN) == 0) {
if (memcmp(&buf[42], "Replica packet",
ETH_HLEN)) {
etdev->ReplicaPhyLoopbkPF = 1;
@@ -939,7 +938,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
* of Multicast address we have, then
* this means we did not find this
* packet's matching address in our
- * list. Set the PacketSize to zero,
+ * list. Set the len to zero,
* so we free our RFD when we return
* from this function.
*/
@@ -963,21 +962,21 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
if (len > 0) {
struct sk_buff *skb = NULL;
- /* rfd->PacketSize = len - 4; */
- rfd->PacketSize = len;
+ /*rfd->len = len - 4; */
+ rfd->len = len;
- skb = dev_alloc_skb(rfd->PacketSize + 2);
+ skb = dev_alloc_skb(rfd->len + 2);
if (!skb) {
dev_err(&etdev->pdev->dev,
"Couldn't alloc an SKB for Rx\n");
return NULL;
}
- etdev->net_stats.rx_bytes += rfd->PacketSize;
+ etdev->net_stats.rx_bytes += rfd->len;
- memcpy(skb_put(skb, rfd->PacketSize),
+ memcpy(skb_put(skb, rfd->len),
rx_local->fbr[rindex]->virt[bindex],
- rfd->PacketSize);
+ rfd->len);
skb->dev = etdev->netdev;
skb->protocol = eth_type_trans(skb, etdev->netdev);
@@ -985,7 +984,7 @@ PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
netif_rx(skb);
} else {
- rfd->PacketSize = 0;
+ rfd->len = 0;
}
nic_return_rfd(etdev, rfd);
@@ -1012,7 +1011,7 @@ void et131x_reset_recv(struct et131x_adapter *etdev)
*/
void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
{
- PMP_RFD rfd = NULL;
+ struct rfd *rfd = NULL;
u32 count = 0;
bool done = true;
@@ -1036,7 +1035,7 @@ void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
*/
if (!etdev->PacketFilter ||
!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) ||
- rfd->PacketSize == 0) {
+ rfd->len == 0) {
continue;
}
@@ -1083,7 +1082,7 @@ static inline u32 bump_fbr(u32 *fbr, u32 limit)
* @etdev: pointer to our adapter
* @rfd: pointer to the RFD
*/
-void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd)
+void nic_return_rfd(struct et131x_adapter *etdev, struct rfd *rfd)
{
struct rx_ring *rx_local = &etdev->rx_ring;
struct rxdma_regs __iomem *rx_dma = &etdev->regs->rxdma;
@@ -1146,10 +1145,10 @@ void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd)
/* The processing on this RFD is done, so put it back on the tail of
* our list
*/
- spin_lock_irqsave(&etdev->RcvLock, flags);
+ spin_lock_irqsave(&etdev->rcv_lock, flags);
list_add_tail(&rfd->list_node, &rx_local->RecvList);
rx_local->nReadyRecv++;
- spin_unlock_irqrestore(&etdev->RcvLock, flags);
+ spin_unlock_irqrestore(&etdev->rcv_lock, flags);
WARN_ON(rx_local->nReadyRecv > rx_local->NumRfd);
}
diff --git a/drivers/staging/et131x/et1310_tx.c b/drivers/staging/et131x/et1310_tx.c
index 0f3473d..4241d2a 100644
--- a/drivers/staging/et131x/et1310_tx.c
+++ b/drivers/staging/et131x/et1310_tx.c
@@ -547,7 +547,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb)
tcb->index_start = etdev->tx_ring.send_idx;
tcb->stale = 0;
- spin_lock_irqsave(&etdev->SendHWLock, flags);
+ spin_lock_irqsave(&etdev->send_hw_lock, flags);
thiscopy = NUM_DESC_PER_RING_TX -
INDEX10(etdev->tx_ring.send_idx);
@@ -613,7 +613,7 @@ static int nic_send_packet(struct et131x_adapter *etdev, struct tcb *tcb)
writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
&etdev->regs->global.watchdog_timer);
}
- spin_unlock_irqrestore(&etdev->SendHWLock, flags);
+ spin_unlock_irqrestore(&etdev->send_hw_lock, flags);
return 0;
}
diff --git a/drivers/staging/et131x/et131x.h b/drivers/staging/et131x/et131x.h
index a8abfe6..8aa3365 100644
--- a/drivers/staging/et131x/et131x.h
+++ b/drivers/staging/et131x/et131x.h
@@ -126,9 +126,9 @@ void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter);
int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter);
void et131x_rx_dma_memory_free(struct et131x_adapter *adapter);
int et131x_rfd_resources_alloc(struct et131x_adapter *adapter,
- struct _MP_RFD *pMpRfd);
+ struct rfd *rfd);
void et131x_rfd_resources_free(struct et131x_adapter *adapter,
- struct _MP_RFD *pMpRfd);
+ struct rfd *rfd);
int et131x_init_recv(struct et131x_adapter *adapter);
void ConfigRxDmaRegs(struct et131x_adapter *adapter);
diff --git a/drivers/staging/et131x/et131x_adapter.h b/drivers/staging/et131x/et131x_adapter.h
index 64a678f..c852f86 100644
--- a/drivers/staging/et131x/et131x_adapter.h
+++ b/drivers/staging/et131x/et131x_adapter.h
@@ -83,21 +83,19 @@
#define LO_MARK_PERCENT_FOR_RX 15
/* RFD (Receive Frame Descriptor) */
-typedef struct _MP_RFD {
+struct rfd {
struct list_head list_node;
- struct sk_buff *Packet;
- u32 PacketSize; /* total size of receive frame */
+ struct sk_buff *skb;
+ u32 len; /* total size of receive frame */
u16 bufferindex;
u8 ringindex;
-} MP_RFD, *PMP_RFD;
+};
-/* Enum for Flow Control */
-typedef enum _eflow_control_t {
- Both = 0,
- TxOnly = 1,
- RxOnly = 2,
- None = 3
-} eFLOW_CONTROL_t, *PeFLOW_CONTROL_t;
+/* Flow Control */
+#define FLOW_BOTH 0
+#define FLOW_TXONLY 1
+#define FLOW_RXONLY 2
+#define FLOW_NONE 3
/* Struct to define some device statistics */
typedef struct _ce_stats_t {
@@ -147,19 +145,6 @@ typedef struct _ce_stats_t {
u32 InterruptStatus;
} CE_STATS_t, *PCE_STATS_t;
-typedef struct _MP_POWER_MGMT {
- /* variable putting the phy into coma mode when boot up with no cable
- * plugged in after 5 seconds
- */
- u8 TransPhyComaModeOnBoot;
-
- /* Next two used to save power information at power down. This
- * information will be used during power up to set up parts of Power
- * Management in JAGCore
- */
- u16 PowerDownSpeed;
- u8 PowerDownDuplex;
-} MP_POWER_MGMT, *PMP_POWER_MGMT;
/* The private adapter structure */
struct et131x_adapter {
@@ -173,19 +158,19 @@ struct et131x_adapter {
u32 HwErrCount;
/* Configuration */
- u8 PermanentAddress[ETH_ALEN];
- u8 CurrentAddress[ETH_ALEN];
+ u8 rom_addr[ETH_ALEN];
+ u8 addr[ETH_ALEN];
bool has_eeprom;
- u8 eepromData[2];
+ u8 eeprom_data[2];
/* Spinlocks */
spinlock_t Lock;
spinlock_t TCBSendQLock;
spinlock_t TCBReadyQLock;
- spinlock_t SendHWLock;
+ spinlock_t send_hw_lock;
- spinlock_t RcvLock;
+ spinlock_t rcv_lock;
spinlock_t RcvPendLock;
spinlock_t FbrLock;
@@ -205,7 +190,7 @@ struct et131x_adapter {
/* Registry parameters */
u8 SpeedDuplex; /* speed/duplex */
- eFLOW_CONTROL_t RegistryFlowControl; /* for 802.3x flow control */
+ u8 wanted_flow; /* Flow we want for 802.3x flow control */
u8 RegistryPhyComa; /* Phy Coma mode enable/disable */
u32 RegistryRxMemEnd; /* Size of internal rx memory */
@@ -214,8 +199,8 @@ struct et131x_adapter {
/* Derived from the registry: */
u8 AiForceDpx; /* duplex setting */
- u16 AiForceSpeed; /* 'Speed', user over-ride of line speed */
- eFLOW_CONTROL_t FlowControl; /* flow control validated by the far-end */
+ u16 AiForceSpeed; /* 'Speed', user over-ride of line speed */
+ u8 flowcontrol; /* flow control validated by the far-end */
enum {
NETIF_STATUS_INVALID = 0,
NETIF_STATUS_MEDIA_CONNECT,
@@ -225,7 +210,19 @@ struct et131x_adapter {
/* Minimize init-time */
struct timer_list ErrorTimer;
- MP_POWER_MGMT PoMgmt;
+
+ /* variable putting the phy into coma mode when boot up with no cable
+ * plugged in after 5 seconds
+ */
+ u8 boot_coma;
+
+ /* Next two used to save power information at power down. This
+ * information will be used during power up to set up parts of Power
+ * Management in JAGCore
+ */
+ u16 pdown_speed;
+ u8 pdown_duplex;
+
u32 CachedMaskValue;
/* Xcvr status at last poll */
diff --git a/drivers/staging/et131x/et131x_initpci.c b/drivers/staging/et131x/et131x_initpci.c
index f62ba7a..50237ac 100644
--- a/drivers/staging/et131x/et131x_initpci.c
+++ b/drivers/staging/et131x/et131x_initpci.c
@@ -131,32 +131,32 @@ void et131x_hwaddr_init(struct et131x_adapter *adapter)
* EEPROM then we need to generate the last octet and set it on the
* device
*/
- if (adapter->PermanentAddress[0] == 0x00 &&
- adapter->PermanentAddress[1] == 0x00 &&
- adapter->PermanentAddress[2] == 0x00 &&
- adapter->PermanentAddress[3] == 0x00 &&
- adapter->PermanentAddress[4] == 0x00 &&
- adapter->PermanentAddress[5] == 0x00) {
+ if (adapter->rom_addr[0] == 0x00 &&
+ adapter->rom_addr[1] == 0x00 &&
+ adapter->rom_addr[2] == 0x00 &&
+ adapter->rom_addr[3] == 0x00 &&
+ adapter->rom_addr[4] == 0x00 &&
+ adapter->rom_addr[5] == 0x00) {
/*
* We need to randomly generate the last octet so we
* decrease our chances of setting the mac address to
* same as another one of our cards in the system
*/
- get_random_bytes(&adapter->CurrentAddress[5], 1);
+ get_random_bytes(&adapter->addr[5], 1);
/*
* We have the default value in the register we are
* working with so we need to copy the current
* address into the permanent address
*/
- memcpy(adapter->PermanentAddress,
- adapter->CurrentAddress, ETH_ALEN);
+ memcpy(adapter->rom_addr,
+ adapter->addr, ETH_ALEN);
} else {
/* We do not have an override address, so set the
* current address to the permanent address and add
* it to the device
*/
- memcpy(adapter->CurrentAddress,
- adapter->PermanentAddress, ETH_ALEN);
+ memcpy(adapter->addr,
+ adapter->rom_addr, ETH_ALEN);
}
}
@@ -193,17 +193,17 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
max_payload &= 0x07; /* Only the lower 3 bits are valid */
if (max_payload < 2) {
- static const u16 AckNak[2] = { 0x76, 0xD0 };
- static const u16 Replay[2] = { 0x1E0, 0x2ED };
+ static const u16 acknak[2] = { 0x76, 0xD0 };
+ static const u16 replay[2] = { 0x1E0, 0x2ED };
if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
- AckNak[max_payload])) {
+ acknak[max_payload])) {
dev_err(&pdev->dev,
"Could not write PCI config space for ACK/NAK\n");
return -EIO;
}
if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
- Replay[max_payload])) {
+ replay[max_payload])) {
dev_err(&pdev->dev,
"Could not write PCI config space for Replay Timer\n");
return -EIO;
@@ -245,12 +245,12 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
for (i = 0; i < ETH_ALEN; i++) {
if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
- adapter->PermanentAddress + i)) {
+ adapter->rom_addr + i)) {
dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
return -EIO;
}
}
- memcpy(adapter->CurrentAddress, adapter->PermanentAddress, ETH_ALEN);
+ memcpy(adapter->addr, adapter->rom_addr, ETH_ALEN);
return 0;
}
@@ -276,11 +276,11 @@ void et131x_error_timer_handler(unsigned long data)
if (!etdev->Bmsr.bits.link_status &&
etdev->RegistryPhyComa &&
- etdev->PoMgmt.TransPhyComaModeOnBoot < 11) {
- etdev->PoMgmt.TransPhyComaModeOnBoot++;
+ etdev->boot_coma < 11) {
+ etdev->boot_coma++;
}
- if (etdev->PoMgmt.TransPhyComaModeOnBoot == 10) {
+ if (etdev->boot_coma == 10) {
if (!etdev->Bmsr.bits.link_status
&& etdev->RegistryPhyComa) {
if ((pm_csr & ET_PM_PHY_SW_COMA) == 0) {
@@ -555,8 +555,8 @@ static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
spin_lock_init(&etdev->Lock);
spin_lock_init(&etdev->TCBSendQLock);
spin_lock_init(&etdev->TCBReadyQLock);
- spin_lock_init(&etdev->SendHWLock);
- spin_lock_init(&etdev->RcvLock);
+ spin_lock_init(&etdev->send_hw_lock);
+ spin_lock_init(&etdev->rcv_lock);
spin_lock_init(&etdev->RcvPendLock);
spin_lock_init(&etdev->FbrLock);
spin_lock_init(&etdev->PHYLock);
@@ -570,7 +570,7 @@ static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
etdev->RegistryJumboPacket = 1514; /* 1514-9216 */
/* Set the MAC address to a default */
- memcpy(etdev->CurrentAddress, default_mac, ETH_ALEN);
+ memcpy(etdev->addr, default_mac, ETH_ALEN);
/* Decode SpeedDuplex
*
@@ -711,7 +711,7 @@ static int __devinit et131x_pci_setup(struct pci_dev *pdev,
INIT_WORK(&adapter->task, et131x_isr_handler);
/* Copy address into the net_device struct */
- memcpy(netdev->dev_addr, adapter->CurrentAddress, ETH_ALEN);
+ memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
/* Setup et1310 as per the documentation */
et131x_adapter_setup(adapter);
@@ -728,7 +728,7 @@ static int __devinit et131x_pci_setup(struct pci_dev *pdev,
/* Initialize variable for counting how long we do not have
link status */
- adapter->PoMgmt.TransPhyComaModeOnBoot = 0;
+ adapter->boot_coma = 0;
/* We can enable interrupts now
*
diff --git a/drivers/staging/et131x/et131x_isr.c b/drivers/staging/et131x/et131x_isr.c
index 36f68fe..ce4d930 100644
--- a/drivers/staging/et131x/et131x_isr.c
+++ b/drivers/staging/et131x/et131x_isr.c
@@ -119,7 +119,7 @@ void et131x_enable_interrupts(struct et131x_adapter *adapter)
u32 mask;
/* Enable all global interrupts */
- if (adapter->FlowControl == TxOnly || adapter->FlowControl == Both)
+ if (adapter->flowcontrol == FLOW_TXONLY || adapter->flowcontrol == FLOW_BOTH)
mask = INT_MASK_ENABLE;
else
mask = INT_MASK_ENABLE_NO_FLOW;
@@ -177,8 +177,8 @@ irqreturn_t et131x_isr(int irq, void *dev_id)
*/
status = readl(&adapter->regs->global.int_status);
- if (adapter->FlowControl == TxOnly ||
- adapter->FlowControl == Both) {
+ if (adapter->flowcontrol == FLOW_TXONLY ||
+ adapter->flowcontrol == FLOW_BOTH) {
status &= ~INT_MASK_ENABLE;
} else {
status &= ~INT_MASK_ENABLE_NO_FLOW;
@@ -295,8 +295,8 @@ void et131x_isr_handler(struct work_struct *work)
/* If the user has flow control on, then we will
* send a pause packet, otherwise just exit
*/
- if (etdev->FlowControl == TxOnly ||
- etdev->FlowControl == Both) {
+ if (etdev->flowcontrol == FLOW_TXONLY ||
+ etdev->flowcontrol == FLOW_BOTH) {
u32 pm_csr;
/* Tell the device to send a pause packet via
@@ -366,7 +366,7 @@ void et131x_isr_handler(struct work_struct *work)
if (status & ET_INTR_PHY) {
u32 pm_csr;
MI_BMSR_t BmsrInts, BmsrData;
- MI_ISR_t myIsr;
+ u16 myisr;
/* If we are in coma mode when we get this interrupt,
* we need to disable it.
@@ -384,12 +384,12 @@ void et131x_isr_handler(struct work_struct *work)
/* Read the PHY ISR to clear the reason for the
* interrupt.
*/
- MiRead(etdev, (uint8_t) offsetof(MI_REGS_t, isr),
- &myIsr.value);
+ MiRead(etdev, (uint8_t) offsetof(struct mi_regs, isr),
+ &myisr);
if (!etdev->ReplicaPhyLoopbk) {
MiRead(etdev,
- (uint8_t) offsetof(MI_REGS_t, bmsr),
+ (uint8_t) offsetof(struct mi_regs, bmsr),
&BmsrData.value);
BmsrInts.value =
diff --git a/drivers/staging/et131x/et131x_netdev.c b/drivers/staging/et131x/et131x_netdev.c
index 106d548..0c298ca 100644
--- a/drivers/staging/et131x/et131x_netdev.c
+++ b/drivers/staging/et131x/et131x_netdev.c
@@ -603,7 +603,7 @@ int et131x_change_mtu(struct net_device *netdev, int new_mtu)
et131x_init_send(adapter);
et131x_hwaddr_init(adapter);
- memcpy(netdev->dev_addr, adapter->CurrentAddress, ETH_ALEN);
+ memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN);
/* Init the device with the new settings */
et131x_adapter_setup(adapter);
generated by cgit v0.10.2 at 2024-09-01 23:29:15 (GMT)