diff options
Diffstat (limited to 'drivers/staging/sm750fb/ddk750_chip.c')
-rw-r--r-- | drivers/staging/sm750fb/ddk750_chip.c | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c index 7b28328..f4975d2 100644 --- a/drivers/staging/sm750fb/ddk750_chip.c +++ b/drivers/staging/sm750fb/ddk750_chip.c @@ -17,7 +17,7 @@ logical_chip_type_t getChipType(void) char physicalRev; logical_chip_type_t chip; - physicalID = devId750;//either 0x718 or 0x750 + physicalID = devId750; /* either 0x718 or 0x750 */ physicalRev = revId750; if (physicalID == 0x718) @@ -257,7 +257,7 @@ int ddk750_initHw(initchip_param_t *pInitParam) unsigned int ulReg; #if 0 - //move the code to map regiter function. + /* move the code to map regiter function. */ if (getChipType() == SM718) { /* turn on big endian bit*/ ulReg = PEEK32(0x74); @@ -285,7 +285,7 @@ int ddk750_initHw(initchip_param_t *pInitParam) ulReg = FIELD_SET(ulReg, VGA_CONFIGURATION, MODE, GRAPHIC); POKE32(VGA_CONFIGURATION, ulReg); } else { -#if defined(__i386__) || defined( __x86_64__) +#if defined(__i386__) || defined(__x86_64__) /* set graphic mode via IO method */ outb_p(0x88, 0x3d4); outb_p(0x06, 0x3d5); @@ -382,7 +382,7 @@ int ddk750_initHw(initchip_param_t *pInitParam) unsigned int absDiff(unsigned int a, unsigned int b) { - if ( a > b ) + if (a > b) return(a - b); else return(b - a); @@ -433,7 +433,7 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) unsigned int RN, quo, rem, fl_quo; unsigned int input, request; unsigned int tmpClock, ret; - pllcalparam * xparm; + pllcalparam *xparm; #if 1 if (getChipType() == SM750LE) { @@ -487,8 +487,6 @@ unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) } } } - - //printk("Finally: pll->n[%lu],m[%lu],od[%lu],pod[%lu]\n",pll->N,pll->M,pll->OD,pll->POD); return ret; } @@ -580,14 +578,9 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */ } /* Restore input frequency from Khz to hz unit */ -// pPLL->inputFreq *= 1000; ulRequestClk *= 1000; pPLL->inputFreq = DEFAULT_INPUT_CLOCK; /* Default reference clock */ - /* Output debug information */ - //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Requested Frequency = %d\n", ulRequestClk)); - //DDKDEBUGPRINT((DISPLAY_LEVEL, "calcPllValue: Input CLK = %dHz, M=%d, N=%d, OD=%d, POD=%d\n", pPLL->inputFreq, pPLL->M, pPLL->N, pPLL->OD, pPLL->POD)); - /* Return actual frequency that the PLL can set */ ret = calcPLL(pPLL); return ret; @@ -616,7 +609,7 @@ unsigned int formatPllReg(pll_value_t *pPLL) | FIELD_VALUE(0, PANEL_PLL_CTRL, N, pPLL->N) | FIELD_VALUE(0, PANEL_PLL_CTRL, M, pPLL->M); - return ulPllReg; + return ulPllReg; } |