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path: root/drivers/usb/host
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Diffstat (limited to 'drivers/usb/host')
-rw-r--r--drivers/usb/host/ehci-fsl.c44
1 files changed, 13 insertions, 31 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index f903521..b15263b 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -284,38 +284,10 @@ static bool usb_phy_clk_valid(struct usb_hcd *hcd,
enum fsl_usb2_phy_modes phy_mode)
{
void __iomem *non_ehci = hcd->regs;
- struct device *dev = hcd->self.controller;
- struct fsl_usb2_platform_data *pdata = dev->platform_data;
bool ret = true;
- int retry = UTMI_PHY_CLK_VALID_CHK_RETRY;
-
- if (phy_mode == FSL_USB2_PHY_ULPI) {
- /* check PHY_CLK_VALID to get phy clk valid */
- if (!(spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
- PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0) ||
- in_be32(non_ehci + FSL_SOC_USB_PRICTRL))) {
- ret = false;
- }
- } else if (phy_mode == FSL_USB2_PHY_UTMI) {
- if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID)) {
- ret = false;
- if (pdata->controller_ver < FSL_USB_VER_2_4) {
- while (retry--) {
- clrbits32(non_ehci + FSL_SOC_USB_CTRL,
- CTRL_UTMI_PHY_EN);
- setbits32(non_ehci + FSL_SOC_USB_CTRL,
- CTRL_UTMI_PHY_EN);
- /* delay required for Clk to appear */
- mdelay(FSL_UTMI_PHY_DLY);
- if ((in_be32(non_ehci +
- FSL_SOC_USB_CTRL) & PHY_CLK_VALID)) {
- ret = true;
- break;
- }
- }
- }
- }
- }
+
+ if (!(in_be32(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
+ ret = false;
return ret;
}
@@ -363,6 +335,16 @@ static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
}
case FSL_USB2_PHY_UTMI_DUAL:
+ /* PHY_CLK_VALID bit is de-featured from all controller
+ * versions below 2.4 and is to be checked only for
+ * internal UTMI phy
+ */
+ if (pdata->controller_ver > FSL_USB_VER_2_4 &&
+ pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
+ pr_err("fsl-ehci: USB PHY clock invalid\n");
+ return -EINVAL;
+ }
+
if (pdata->have_sysif_regs && pdata->controller_ver) {
/* controller version 1.6 or above */
clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,