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-rw-r--r--include/asm-ia64/acpi.h4
-rw-r--r--include/asm-ia64/asmmacro.h11
-rw-r--r--include/asm-ia64/machvec_dig.h2
-rw-r--r--include/asm-ia64/numa.h2
-rw-r--r--include/asm-ia64/numnodes.h13
-rw-r--r--include/asm-ia64/page.h2
-rw-r--r--include/asm-ia64/pal.h3
-rw-r--r--include/asm-ia64/processor.h1
-rw-r--r--include/asm-ia64/sn/l1.h3
-rw-r--r--include/asm-ia64/sn/pcibr_provider.h1
-rw-r--r--include/asm-ia64/sn/pcidev.h1
-rw-r--r--include/asm-ia64/sn/sn_feature_sets.h3
-rw-r--r--include/asm-ia64/sn/sn_sal.h26
13 files changed, 47 insertions, 25 deletions
diff --git a/include/asm-ia64/acpi.h b/include/asm-ia64/acpi.h
index f7a5176..d734585 100644
--- a/include/asm-ia64/acpi.h
+++ b/include/asm-ia64/acpi.h
@@ -111,7 +111,11 @@ extern int additional_cpus;
#ifdef CONFIG_ACPI_NUMA
/* Proximity bitmap length; _PXM is at most 255 (8 bit)*/
+#ifdef CONFIG_IA64_NR_NODES
+#define MAX_PXM_DOMAINS CONFIG_IA64_NR_NODES
+#else
#define MAX_PXM_DOMAINS (256)
+#endif
extern int __devinitdata pxm_to_nid_map[MAX_PXM_DOMAINS];
extern int __initdata nid_to_pxm_map[MAX_NUMNODES];
#endif
diff --git a/include/asm-ia64/asmmacro.h b/include/asm-ia64/asmmacro.h
index 77af457..d4cec32 100644
--- a/include/asm-ia64/asmmacro.h
+++ b/include/asm-ia64/asmmacro.h
@@ -51,6 +51,17 @@ name:
[99:] x
/*
+ * Tag MCA recoverable instruction ranges.
+ */
+
+ .section "__mca_table", "a" // declare section & section attributes
+ .previous
+
+# define MCA_RECOVER_RANGE(y) \
+ .xdata4 "__mca_table", y-., 99f-.; \
+ [99:]
+
+/*
* Mark instructions that need a load of a virtual address patched to be
* a load of a physical address. We use this either in critical performance
* path (ivt.S - TLB miss processing) or in places where it might not be
diff --git a/include/asm-ia64/machvec_dig.h b/include/asm-ia64/machvec_dig.h
index 4dc8522..8a0752f 100644
--- a/include/asm-ia64/machvec_dig.h
+++ b/include/asm-ia64/machvec_dig.h
@@ -2,7 +2,6 @@
#define _ASM_IA64_MACHVEC_DIG_h
extern ia64_mv_setup_t dig_setup;
-extern ia64_mv_irq_init_t dig_irq_init;
/*
* This stuff has dual use!
@@ -13,6 +12,5 @@ extern ia64_mv_irq_init_t dig_irq_init;
*/
#define platform_name "dig"
#define platform_setup dig_setup
-#define platform_irq_init dig_irq_init
#endif /* _ASM_IA64_MACHVEC_DIG_h */
diff --git a/include/asm-ia64/numa.h b/include/asm-ia64/numa.h
index 3ae128f..dae6aeb 100644
--- a/include/asm-ia64/numa.h
+++ b/include/asm-ia64/numa.h
@@ -23,7 +23,7 @@
#include <asm/mmzone.h>
-extern u8 cpu_to_node_map[NR_CPUS] __cacheline_aligned;
+extern u16 cpu_to_node_map[NR_CPUS] __cacheline_aligned;
extern cpumask_t node_to_cpu_mask[MAX_NUMNODES] __cacheline_aligned;
/* Stuff below this line could be architecture independent */
diff --git a/include/asm-ia64/numnodes.h b/include/asm-ia64/numnodes.h
index 21cff4d..e9d356f 100644
--- a/include/asm-ia64/numnodes.h
+++ b/include/asm-ia64/numnodes.h
@@ -3,13 +3,18 @@
#ifdef CONFIG_IA64_DIG
/* Max 8 Nodes */
-#define NODES_SHIFT 3
+# define NODES_SHIFT 3
#elif defined(CONFIG_IA64_HP_ZX1) || defined(CONFIG_IA64_HP_ZX1_SWIOTLB)
/* Max 32 Nodes */
-#define NODES_SHIFT 5
+# define NODES_SHIFT 5
#elif defined(CONFIG_IA64_SGI_SN2) || defined(CONFIG_IA64_GENERIC)
-/* Max 256 Nodes */
-#define NODES_SHIFT 8
+# if CONFIG_IA64_NR_NODES == 256
+# define NODES_SHIFT 8
+# elif CONFIG_IA64_NR_NODES <= 512
+# define NODES_SHIFT 9
+# elif CONFIG_IA64_NR_NODES <= 1024
+# define NODES_SHIFT 10
+# endif
#endif
#endif /* _ASM_MAX_NUMNODES_H */
diff --git a/include/asm-ia64/page.h b/include/asm-ia64/page.h
index 3ab27333..6e9aa23 100644
--- a/include/asm-ia64/page.h
+++ b/include/asm-ia64/page.h
@@ -149,7 +149,7 @@ typedef union ia64_va {
| (REGION_OFFSET(x) >> (HPAGE_SHIFT-PAGE_SHIFT)))
# define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
# define is_hugepage_only_range(mm, addr, len) \
- (REGION_NUMBER(addr) == RGN_HPAGE && \
+ (REGION_NUMBER(addr) == RGN_HPAGE || \
REGION_NUMBER((addr)+(len)-1) == RGN_HPAGE)
extern unsigned int hpage_shift;
#endif
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 7708ec6..4e7e6f2 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -1640,8 +1640,7 @@ ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
if (iprv.status == PAL_STATUS_SUCCESS)
{
- if (proc_number == 0)
- mapping->overview.overview_data = iprv.v0;
+ mapping->overview.overview_data = iprv.v0;
mapping->ppli1.ppli1_data = iprv.v1;
mapping->ppli2.ppli2_data = iprv.v2;
}
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
index 128fefd..b3bd58e 100644
--- a/include/asm-ia64/processor.h
+++ b/include/asm-ia64/processor.h
@@ -181,7 +181,6 @@ DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
#define local_cpu_data (&__ia64_per_cpu_var(cpu_info))
#define cpu_data(cpu) (&per_cpu(cpu_info, cpu))
-extern void identify_cpu (struct cpuinfo_ia64 *);
extern void print_cpu_info (struct cpuinfo_ia64 *);
typedef struct {
diff --git a/include/asm-ia64/sn/l1.h b/include/asm-ia64/sn/l1.h
index e3b8191..344bf44 100644
--- a/include/asm-ia64/sn/l1.h
+++ b/include/asm-ia64/sn/l1.h
@@ -34,6 +34,8 @@
#define L1_BRICKTYPE_IA 0x6b /* k */
#define L1_BRICKTYPE_ATHENA 0x2b /* + */
#define L1_BRICKTYPE_DAYTONA 0x7a /* z */
+#define L1_BRICKTYPE_1932 0x2c /* . */
+#define L1_BRICKTYPE_191010 0x2e /* , */
/* board type response codes */
#define L1_BOARDTYPE_IP69 0x0100 /* CA */
@@ -46,5 +48,4 @@
#define L1_BOARDTYPE_DAYTONA 0x0800 /* AD */
#define L1_BOARDTYPE_INVAL (-1) /* invalid brick type */
-
#endif /* _ASM_IA64_SN_L1_H */
diff --git a/include/asm-ia64/sn/pcibr_provider.h b/include/asm-ia64/sn/pcibr_provider.h
index a601d3a..51260ab 100644
--- a/include/asm-ia64/sn/pcibr_provider.h
+++ b/include/asm-ia64/sn/pcibr_provider.h
@@ -144,4 +144,5 @@ extern int sal_pcibr_slot_enable(struct pcibus_info *soft, int device,
void *resp);
extern int sal_pcibr_slot_disable(struct pcibus_info *soft, int device,
int action, void *resp);
+extern u16 sn_ioboard_to_pci_bus(struct pci_bus *pci_bus);
#endif
diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h
index 38cdffb..eac3561 100644
--- a/include/asm-ia64/sn/pcidev.h
+++ b/include/asm-ia64/sn/pcidev.h
@@ -76,6 +76,7 @@ extern void sn_pci_controller_fixup(int segment, int busnum,
struct pci_bus *bus);
extern void sn_bus_store_sysdata(struct pci_dev *dev);
extern void sn_bus_free_sysdata(void);
+extern void sn_generate_path(struct pci_bus *pci_bus, char *address);
extern void sn_pci_fixup_slot(struct pci_dev *dev);
extern void sn_pci_unfixup_slot(struct pci_dev *dev);
extern void sn_irq_lh_init(void);
diff --git a/include/asm-ia64/sn/sn_feature_sets.h b/include/asm-ia64/sn/sn_feature_sets.h
index ff33e3b..30dcfa4 100644
--- a/include/asm-ia64/sn/sn_feature_sets.h
+++ b/include/asm-ia64/sn/sn_feature_sets.h
@@ -30,8 +30,7 @@ extern int sn_prom_feature_available(int id);
#define PRF_PAL_CACHE_FLUSH_SAFE 0
#define PRF_DEVICE_FLUSH_LIST 1
-
-
+#define PRF_HOTPLUG_SUPPORT 2
/* --------------------- OS Features -------------------------------*/
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index b546de2..244449d 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -907,18 +907,22 @@ ia64_sn_sysctl_tio_clock_reset(nasid_t nasid)
/*
* Get the associated ioboard type for a given nasid.
*/
-static inline int
-ia64_sn_sysctl_ioboard_get(nasid_t nasid)
+static inline s64
+ia64_sn_sysctl_ioboard_get(nasid_t nasid, u16 *ioboard)
{
- struct ia64_sal_retval rv;
- SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_IOBOARD,
- nasid, 0, 0, 0, 0, 0);
- if (rv.v0 != 0)
- return (int)rv.v0;
- if (rv.v1 != 0)
- return (int)rv.v1;
-
- return 0;
+ struct ia64_sal_retval isrv;
+ SAL_CALL_REENTRANT(isrv, SN_SAL_SYSCTL_OP, SAL_SYSCTL_OP_IOBOARD,
+ nasid, 0, 0, 0, 0, 0);
+ if (isrv.v0 != 0) {
+ *ioboard = isrv.v0;
+ return isrv.status;
+ }
+ if (isrv.v1 != 0) {
+ *ioboard = isrv.v1;
+ return isrv.status;
+ }
+
+ return isrv.status;
}
/**
generated by cgit v0.10.2 at 2024-11-15 16:53:24 (GMT)