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2017-09-25arm64: dts: add OH ports on LS1043/46Iordache Florinel-R70177
Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
2017-09-25arm64: dts: ls1021/ls1043/ls1046: add qdma nodesjiaheng.fan
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
2017-09-25arm64: dts: ls1088a: Add flash node for ls1088a qds and rdbPrabhakar Kushwaha
LS1088AQDS consist of NOR, NAND and FPGA connected over IFC LS1088ARDB consist of NAND and FPGA connected over IFC. So add flash information in ifc node of device tree. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-09-25arm64: dts: ls208xa: Add QSPI Flash node for RDBSuresh Gupta
This is temporary patch, will rewrite for open source Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
2017-09-25arm64: dts: ls2081ardb: Add DTS support for NXP LS2081ARDBPriyanka Jain
This patch add support for NXP LS2081ARDB board which has LS2081A SoC. LS2081A SoC is 40-pin derivative of LS2088A SoC So, from functional perspective both are same. Hence,ls2088a SoC dtsi files are included from ls2081ARDB dts Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2017-09-25arm64: dts: add iommu-map property in fsl-mc nodeNipun Gupta
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
2017-09-25crypto: caam/qi2 - setup CG only if supportedHoria Geantă
Even if MC f/w has support for DPSECI Congestion Group (CG), we still have to check whether the dpseci object has been created with this capability before setting it up. Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-09-25crypto: caam/qi2 - add dpseci capabilities supportHoria Geantă
Starting with MC firmware 10.2.0 (*), support has been added to obtain the properties of dpseci objects, such as Congestion Group or Order Preservation. (*) DPSECI object (API) version has not bumped, it's still v5.1; this makes it harder to offer backwards compatibility. Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-09-25crypto: caam/qi2 - fix authenc givencrypt shared descriptorHoria Geantă
authenc givencrypt shared descriptor is being saved in the wrong buffer, i.e. flc[GIVENCRYPT]. For authenc, since .encrypt and .givencrypt cannot coexist: -the same flc[ENCRYPT] buffer is used for the shared descriptor and -flc[GIVENCRYPT] is not used Fixes: 1417145b769f ("crypto: caam/qi2 - add DPAA2-CAAM driver") Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-09-25drivers: firmware: psci: use psci v0.2 to implement sleepYuantian Tang
Technically psci v0.2 can not support system sleep. Unfortunately our PPA only supports psci v0.2. So workaround this by changing psci v1.0 to v0.2 call to implement system sleep. Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
2017-09-25QE: splitted patch from QE for irqZhao Qiang
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25arm64: dts: ls2088a: add cpu idle supportYuantian Tang
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
2017-09-25arm64: dts: ls1088a: add cpu idle supportYuantian Tang
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
2017-09-25dts: ls1021a: update the clockgen nodeYuantian Tang
qoriq clock driver has been updated to parse the clock configuration information defined in driver itself not in dts. Since the new implementation and the bindings have been merged, it is time to update the clock related node and remove redundent clock configuration information from the dts. Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
2017-09-25arm64: dts: ls1088a: Add USB supportyinbo.zhu
Fix the issue that usb is not detected on ls1088ardb Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2017-09-25config: enable support for lxd and lxd-bridgeIoana Ciornei
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
2017-09-25multi_v7_defconfig: added config options required for DPAA 1Madalin Bucur
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
2017-09-25lsdk.config: added config options required to run dockerIoana Ciornei
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
2017-09-25add restool ioctl entry to DocumentationIoana Ciornei
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
2017-09-25arm: config: Remove CONFIG_MTD_CFI_BE_BYTE_SWAP in multi_v7_defconfigAlison Wang
For the patch to update struct map_info's swap field based on device characteristics defined in device tree, CONFIG_MTD_CFI_BE_BYTE_SWAP is not used. This patch will remove it in multi_v7_defconfig. Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-09-25arm64: configs: Remove CONFIG_MTD_CFI_BE_BYTE_SWAP in lsdk.configAlison Wang
For the patch to update struct map_info's swap field based on device characteristics defined in device tree, CONFIG_MTD_CFI_BE_BYTE_SWAP is not used. This patch will remove it in lsdk.config. Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-09-25config: arm32: enable necessary options for KVM and containersIoana Ciornei
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
2017-09-25arm64:configs: Enable CEPH_FS and XFS_FS in lsdk.configShengzhou Liu
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2017-09-25arm64: lsdk.config: Enable CONFIG_OVERLAY_FS in kernelShengzhou Liu
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2017-09-25arm: configs: Add lsdk.config for arm32 in lsdkShengzhou Liu
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2017-09-25arm64: defconfig: Enable CONFIG_FHANDLEShengzhou Liu
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2017-09-25config: multiv8: enable CONFIG_FSL_SDK_DPA insteadZhao Qiang
enable CONFIG_FSL_SDK_DPA instead of CONFIG_HAS_FSL_QBMAN for 32b os on arm64 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25vfio: fsl-mc: enable CONFIG_VFIO_FSL_MC for arm64 defconfigZhao Qiang
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25config: splitted config part from QEZhao Qiang
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25arm64: defconfig: Enable SAI and eDMA supportAlison Wang
This patch adds SAI and eDMA support in the defconfig. Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-09-25pcie-ep: Fix the memory leak issueLiu Gang
Add the memory free step to avoid the memory leak issue. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-25pci-ep/ls1046a: Add new interface to show the transfer dataLiu Gang
Add a "dump" interface to show the PCI transfer data. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-25pci-ep/ls1046a: Instead of the __get_free_pages with dma_alloc_coherentLiu Gang
For more usability, instead of the the __get_free_pages with dma_alloc_coherent to ensure the data's cache coherent from PCI port to DDR memroy space. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-25pci-ep/ls1046a: Add new input parameter to set transfer dataLiu Gang
Add a new input parameter for PCI-EP test to set the different transfer data for each test time. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-25pci-ep/ls1046a: Remove the BARs set stepLiu Gang
The BARs has been set in u-boot, so in kernel it does not need to be set again. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-25pci-ep/ls1046a: Correct LUT offset for different LS platformLiu Gang
There are different LUT offsets for different LS platforms. Adding a private struct for each LS platform in the of_device_id struct to bring in the specific LUT offset for the LS platform. Signed-off-by: Liu Gang <Gang.Liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-25pci/layerscape: add msi trigger functionMinghuan Lian
The patch gets the MSI message address and data from MSI capability and creates an outbound window to map MSI message address. So writing data to this window will trigger a MSI interrupt. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-25pci/layerscape: fix compile issueMingkai Hu
WARNING: drivers/built-in.o(.data+0x1024): Section mismatch in reference from the variable ls_pcie_ep_driver to the function .init.text:ls_pcie_ep_probe() The variable ls_pcie_ep_driver references the function __init ls_pcie_ep_probe() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console drivers/built-in.o: In function `ls_pcie_ep_test_thread': :(.text+0x1528a): undefined reference to `__aeabi_uldivmod' :(.text+0x153a4): undefined reference to `__aeabi_uldivmod' make: *** [vmlinux] Error 1 Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-25pci/layerscape: Add PCIe endpoint driverMinghuan Lian
This driver is for Layerscape PCIe endpoint driver. It provides "regs" "test" debug file operations. "regs" read operation can dump the controller register; writer can change register value. "test" includes "init", "dma", "cpy", "free" commands which are used to test DMA and memcpy EP performance. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-09-25add ETH_MIN_MTUZhao Qiang
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25dma: fsl-qdma: remove select ARCH_DMA_ADDR_T_64BIT in driver/dma/Kconfigjiaheng.fan
There is a mistake operation that select ARCH_DMA_ADDR_T_64BIT was taken to error location. Now ARCH_DMA_ADDR_T_64BIT is unnecessary, so it is removed. Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
2017-09-25dma: fsl-dpaa-qdma: support fsl-mc IOVA addrjiaheng.fan
fsl-mc works on IOVA addr if enabling smmu, otherwise it works on physics addr. Add judgement of smmu status, dpaa2-qdma will disalbe BMT bit in qdma-fd and qdma-list-table if enabling smmu. Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
2017-09-25dma: fsl-dpaa-qdma: support qDMA from LS2 rev2jiaheng.fan
Update qDMA driver to work with qDMA IP ver 1.1 from LS2 rev2. The driver is still compatible with IP v1.0 from rev1. Set the transaction type for command field for both source and destination descriptors to coherent copy of cacheable memory. Don't enable source prefetchable (SPF) in IP v1.0 FD since it overlaps with IP v1.1 source read transaction QoS field. Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com> Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
2017-09-25dma: fsl-dpaa-qdma: update dpdmai command ids set for MC v10.xjiaheng.fan
Update dpdmai command ids in order to work with MC 10.0.0. The binary interface compatibility is maintained with MC v9.x. Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com> Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
2017-09-25dma: fsl-dpaa-qdma: dpaa2 qdma supportjiaheng.fan
Support basic feature and scatter gather. Up to 8 channels are supported. Multi-threads per channel are supported. Note: For multi-threads per channel, the latter work may be completed first. Signed-off-by: Changming Huang <jerry.huang@nxp.com> Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
2017-09-25dma: fsl-qdma: set LWC to 0b10jiaheng.fan
LWC = 0b10: The last write is a posted write chased with a non-prefetchable read. The read size is the same as last write when write size < 4B or 4B otherwise. Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
2017-09-25dma: fsl-qdma: Pre-request full command descriptor for enqueue.jiaheng.fan
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
2017-09-25dma: fsl-qdma: add workaround for TKT329166jiaheng.fan
The qDMA completion queue has a Status Enqueue Required (SER) bit per entry to indicate if a DMA job needs to enqueue over the QMan DCP portal. This bit is first set when the completion queue entry is allocated and the descriptor SER bit is also set. An entry is ready to be enqueued when the DMA engine completes the DMA transfer for that job. After a completion entry enqueues, the SER bit is cleared to indicate that the entry can be removed which is done by shifting the queue. It is possible that an earlier allocated entry is ready to shift (enqueued previous cycle) while an entry is performing an enqueue which requires clearing the SER bit next cycle. During the shift of the queue, the SER bit is not cleared properly and will remain set which causes an additional enqueue to occur for the same job. Workaround: In the software, if the duplicate status notification is seen, then discard it (calling “check duplicate status and discard” ). Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
2017-09-25dma: fsl-qdma: uniform distribute the channels to all the commandjiaheng.fan
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
2017-09-25dma: fsl-qdma: rectify the address for some registerjiaheng.fan
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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