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2016-02-29Merge tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi into ↵Arnd Bergmann
next/dt64 Merge "ARM64: DT: Hisilicon Hip05 soc and D02 board updates for 4.6" from Wei Xu: - Add L2 cache topology - Use Cortex specific device node for pmu - Append all gicv3 ITS entries - Append gpio nodes - Append power button node for D02 board * tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi: arm64: dts: hip05: Append power button node for D02 board arm64: dts: hip05: Append gpio nodes arm64: dts: hip05: Append all gicv3 ITS entries arm64: dts: hip05: Use Cortex specific device node for pmu arm64: dts: hip05: Add L2 cache topology
2016-02-29Merge tag 'renesas-arm64-dt2-for-v4.6' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64 Merge "Second Round of Renesas ARM64 Based SoC DT Updates for v4.6" from Simon Horman: Updates for r8a7795/salvator-x * Enable USB2.0, and SDHI0 & 3 * Add GIC-400 virtual interfaces * Add INTC-EX and L2 cache-controller nodes * Use fallback etheravb compatibility string * Use GIC_* defines where appropriate * tag 'renesas-arm64-dt2-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2 arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2 arm64: dts: r8a7795: add USB2.0 Host (EHCI/OHCI) device nodes arm64: dts: r8a7795: add usb2_phy device nodes arm64: dts: r8a7795: use fallback etheravb compatibility string arm64: dts: r8a7795: salvator-x: enable SDHI0 & 3 arm64: dts: r8a7795: Add SDHI support to dtsi arm64: dts: r8a7795: Add GIC-400 virtual interfaces arm64: dts: r8a7795: Add INTC-EX device node arm64: dts: r8a7795: Add CA53 L2 cache-controller node arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node arm64: dts: r8a7795: use GIC_* defines arm64: dts: r8a7795: pmu: switch to Cortex specific device nodes arm64: dts: r8a7795: Add L2 cache-controller nodes
2016-02-26Merge tag 'arm-soc/for-4.6/devicetree-arm64' of ↵Arnd Bergmann
http://github.com/Broadcom/stblinux into next/dt64 Merge "Broadcom devicetree-arm64 changes for 4.6" from Florian Fainelli: This pull request contains Broadcom ARM64-based SoCs device tree changes: - Anup adds additional nodes to the Broadcom Northstart 2 Device Trees: SDHCI (iProc-compatible), ARM SP804 timers, ARM SP805 watchdog - Anup also adds a binding documentation for the ARM SP805 watchdog since there was not one in tree before - Ray adds PCIE root complex nodes to the Northstar 2 Device Tree nodes, using the iProc-compatible binding - Jayachandran C. adds binding documentation for the Broadcom Vulcan processors and reference platforms * tag 'arm-soc/for-4.6/devicetree-arm64' of http://github.com/Broadcom/stblinux: dt-bindings: Add documentation for Broadcom Vulcan arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2 arm64: dts: Add ARM SP805 watchdog DT node for NS2 dt-bindings: watchdog: Add ARM SP805 DT bindings arm64: dts: Add ARM SP804 timer DT nodes for NS2 arm64: dts: Add SDHCI DT node for NS2
2016-02-26arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsiAntoine Tenart
Following the addition of the Alpine MSIX controller driver, add the corresponding node in the Alpine v2 device tree. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-26arm64: dts: add the Alpine v2 EVPAntoine Tenart
This patch adds the initial support for the Alpine v2 EVP board from Annapurna Labs (Amazon). Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Barak Wasserstrom <barak@annapurnalabs.com> Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-26Merge tag 'zynqmp-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx into ↵Arnd Bergmann
next/dt64 Merge "ARM: Xilinx ZynqMP dt patches for v4.6" from Michal Simek: - Extract clock information from EP108 - Sort GPIO node * tag 'zynqmp-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx: ARM64: zynqmp: Extract clock information from EP108 ARM64: zynqmp: Keep gpio node alphabetically sorted
2016-02-26Merge tag 'v4.5-next-dts64' of https://github.com/mbgg/linux-mediatek into ↵Arnd Bergmann
next/dt64 Merge "ARM: mediatek: dts updates for v4.6" from Matthias Brugger: Add nor-flash to mt8173 SoC. Add efuse device to mt8173 SoC. Fix power-domain issue mt8173-evb which uses older chip revision. * tag 'v4.5-next-dts64' of https://github.com/mbgg/linux-mediatek: ARM64: dts: Mediatek: mt8173-evb: fix access MMC fail issue dts: arm64: Add EFUSE device node arm64: dts: mt8173: Add nor flash node
2016-02-25arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2Yoshihiro Shimoda
We should set SW15 to pin 2-3 side on the board before we use CN9 as USB host or peripheral. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-25arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2Yoshihiro Shimoda
This board has a MAX3355 chip. However, we cannot use the extcon/max3355 driver because the ID pin doesn't connect to a gpio pin (in other words, it connects to the SoC specific pin). And, the phy-rcar-gen3-usb2 driver cannot handle such a chip for now. So, this patch enables usb2_phy of channel 1 and 2. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-25arm64: dts: r8a7795: add USB2.0 Host (EHCI/OHCI) device nodesYoshihiro Shimoda
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-25arm64: dts: r8a7795: add usb2_phy device nodesYoshihiro Shimoda
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-25arm64: dts: r8a7795: use fallback etheravb compatibility stringSimon Horman
Use recently added fallback compatibility string in r8a7795 device tree. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-25arm64: dts: r8a7795: salvator-x: enable SDHI0 & 3Ai Kyuse
Add the exposed SD card slots. The on-board eMMC needs to wait until we fixed the 8bit support. Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-25arm64: dts: r8a7795: Add SDHI support to dtsiAi Kyuse
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [wsa: squashed some fixes and added mmc-caps] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-25arm64: dts: hip05: Append power button node for D02 boardKefeng Wang
This patch adds poweroff button device node to support poweroff feature on hip05 d02 board. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25arm64: dts: hip05: Append gpio nodesKefeng Wang
There are two dw GPIO controllers in hip05 peri sub, this patch adds the corresponding device tree nodes. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25arm64: dts: hip05: Append all gicv3 ITS entriesKefeng Wang
There are four subsystems in hip05 soc, peri/m3/pcie/dsa, each subsystem has one its, append them under gicv3 node. They will be used by hisilicon mbigen. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25arm64: dts: hip05: Use Cortex specific device node for pmuKefeng Wang
Instead of using the generic armv8-pmuv3 compatibility, use the more specific Cortex A57 compatibility. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25arm64: dts: hip05: Add L2 cache topologyKefeng Wang
The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus share one L2 cache, add them to the dtsi file so that the cache hierarchy can be probed. Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25ARM64: zynqmp: Extract clock information from EP108Michal Simek
Extract clocks and put it specific file to help with platform autogeneration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-25ARM64: zynqmp: Keep gpio node alphabetically sortedMichal Simek
No functional change. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-25Merge tag 'mvebu-dt64-4.6-1' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson
next/dt64 mvebu dt64 for 4.6 (part 1) Device tree part of the Armada 3700 support: - binding for the Armada 3700 SoCs - device tree files for the SoCs and a board - tidy up the Marvell related files * tag 'mvebu-dt64-4.6-1' of git://git.infradead.org/linux-mvebu: arm64: dts: add the Marvell Armada 3700 family and a development board devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC family Documentation: dt: Tidy up the Marvell related files Documentation: dt-bindings: Add a new compatible for the Armada 3700 Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24arm64: dts: amd: Fix-up for ccn504 and kcs nodesSuravee Suthikulpanit
This is a fix-up patch based on the review comment from Arnd regarding: * fix ccn504 address in the node name * remove kcs interrupt-name Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24Merge tag 'v4.6-rockchip-dts64-1' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64 Define the tuning-related mmc clocks and move from gpio-key,wakeup to the more generic wakeup-source property. * tag 'v4.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: replace gpio-key,wakeup with wakeup-source property arm64: dts: rockchip: add rk3368 tuning clk for emmc and sdmmc Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-20dt-bindings: Add documentation for Broadcom VulcanJayachandran C
Update arm/cpus.txt to add "brcm,vulcan" CPU. Add documentation for Broadcom Vulcan boards in arm/bcm/brcm,vulcan-soc.txt Signed-off-by: Jayachandran C <jchandra@broadcom.com>
2016-02-19ARM64: dts: Mediatek: mt8173-evb: fix access MMC fail issueEddie Huang
MT8173 E1 chip has one bug that if turn off USB power domain, vcore power will also be off, thus cause modules using vcore power domain fail, like MMC. The E1 chip only found on MT8173-evb board and this board only has E1 chip, so implement this as a board specific workaround. Pwrapper use vcore power, so add pwrapper using USB power domain to keep USB power domain not to zero and disabled. Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19arm64: dts: r8a7795: Add GIC-400 virtual interfacesDirk Behme
Besides the distributor and the CPU interface the GIC-400 additionally supports the virtual interface control blocks and the virtual CPU interfaces. Add the physical base addresses and size for these. See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0471b/index.html -> 3.2. GIC-400 register map and Linux kernel's Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt for more details. For the at GICH Virtual interface control blocks at 0xf1040000 cover the whole 128kB (0x20000) range. This is done based on the advice from Marc Zyngier http://www.spinics.net/lists/arm-kernel/msg483139.html Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-17arm64: dts: add the Marvell Armada 3700 family and a development boardGregory CLEMENT
Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53 CPUs. There are two members in this family: the Armada 3710 (Single CPU) and the Armada 3720 (Dual CPUs). It also adds a dts file for the Marvell Armada 3720 DB board. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-02-17devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC familyGregory CLEMENT
The Marvell Armada 3700 is a family of ARMv8 CA53 SoCs. This commit introduces the Device Tree binding that documents the top-level compatible strings for Armada 3700 based platforms. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org>
2016-02-17Documentation: dt: Tidy up the Marvell related filesGregory CLEMENT
Over the last releases we have added more and more Marvell related binding directly in the arm directory. It's time to have our proper directory inside it, and move all the files in it. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org>
2016-02-17Documentation: dt-bindings: Add a new compatible for the Armada 3700Gregory CLEMENT
The AHCI interfaces used in the Armada 3700 has a few differences with the one used in the Armada 38x, so it deserves its own compatible string. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org>
2016-02-17arm64: dts: r8a7795: Add INTC-EX device nodeMagnus Damm
Add a single r8a7795 INTC-EX device node to support external IRQ pins IRQ0 -> IRQ5. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-17arm64: dts: r8a7795: Add CA53 L2 cache-controller nodeGeert Uytterhoeven
Add a device node for the Cortex-A53 L2 cache-controller. The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-17arm64: dts: r8a7795: Add missing properties to CA57 L2 cache nodeGeert Uytterhoeven
Add the missing "cache-unified" and "cache-level" properties to the Cortex-A57 cache-controller node. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-15arm64: dts: r8a7795: use GIC_* definesSimon Horman
Use GIC_* defines for GIC interrupt cells in r8a7795 device tree. Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-12arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2Ray Jui
This patch enables PCIe0 and PCIe4 for NS2 by adding appropriate DT nodes in NS2 DT. Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-12arm64: dts: Add ARM SP805 watchdog DT node for NS2Anup Patel
We have one ARM SP805 watchdog instance on NS2 for non-secure software hence this patch adds appropriate watchdog DT node in NS2 DT. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Pramod KUMAR <pramodku@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-12dt-bindings: watchdog: Add ARM SP805 DT bindingsAnup Patel
The ARM SP805 DT node is already present in various DTS files. This patch adds missing DT bindings documentation for ARM SP805. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Vikram Prakash <vikramp@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-12arm64: dts: Add ARM SP804 timer DT nodes for NS2Anup Patel
We have four ARM SP804 dual-mode timer instances in NS2 SoC hence this patch adds appropriate DT nodes for NS2. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Pramod KUMAR <pramodku@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-12arm64: dts: Add SDHCI DT node for NS2Anup Patel
The IPROC SDHCI driver works fine for SDIO 3.0 on NS2 so let's enable it for NS2 SoC in NS2 DT. Signed-off-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Vikram Prakash <vikramp@broadcom.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-11dts: arm64: Add EFUSE device nodeandrew-ct.chen@mediatek.com
Add Mediatek MT8173 EFUSE device node Signed-off-by: Andrew-CT Chen <andrew-ct.chen@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-11arm64: dts: mt8173: Add nor flash nodeBayi Cheng
Add Mediatek nor flash node Signed-off-by: Bayi Cheng <bayi.cheng@mediatek.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium. org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-09arm64: dts: rockchip: replace gpio-key,wakeup with wakeup-source propertySudeep Holla
Keyboard driver for GPIO buttons(gpio-keys) checks for the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source. Few dts files assign value "1" to gpio-key,wakeup and in one instance a value "0" is assigned probably assuming it won't be enabled as a wakeup source. Since the presence of the boolean property indicates it is enabled, value of "0" have no value. This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property which inturn fixes the above mentioned issue. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-02-08Merge tag 'renesas-arm64-dt-for-v4.6' of ↵Olof Johansson
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64 Renesas ARM64 Based SoC DT Updates for v4.6 * Use SCIF fallback compatibility strings * Add Baud Rate Generator (BRG) support for (H)SCIF * Enable SCIF_CLK frequency and pins * Enable USB 3.0 host * Add Add USB-DMAC device nodes * Complete SYS-DMAC device nodes * tag 'renesas-arm64-dt-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: dts: salvator-x: Enable SCIF_CLK frequency and pins arm64: dts: r8a7795: Add BRG support for (H)SCIF arm64: dts: r8a7795: Rename the serial port clock to fck arm64: dts: r8a7795: Add SCIF fallback compatibility strings arm64: dts: r8a7795: Add USB-DMAC device nodes arm64: dts: salvator-x: enable usb3.0 host channel 0 arm64: dts: r8a7795: Add USB3.0 host device nodes arm64: dts: r8a7795: Complete SYS-DMAC nodes Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Add support for AMD/Linaro 96Boards Enterprise Edition Server boardSuravee Suthikulpanit
Add device tree file for AMD/Linaro 96Boards Enterprise Edition Server (Husky) Board. This is based on the AMD Seattle Rev.B0 system Signed-off-by: Leo Duran <leo.duran@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Add support for new AMD Overdrive boardsSuravee Suthikulpanit
Add device tree files for AMD Overdrive boards which comes with AMD Seattle Revision B0 and B1 SOCs. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Add AMD XGBE device tree fileTom Lendacky
Add AMD XGBE device tree file, which is available in AMD Seattle RevB. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Add KCS device tree nodeBrijesh Singh
Add KCS device node to support IPMI solution on Overdrive system. Signed-off-by: Brijesh Singh <brijeshkumar.singh@amd.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Add PERF CCN-504 device tree nodeSuravee Suthikulpanit
Add PERF CCN-504 device tree node. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-08dtb: amd: Misc changes for GPIO devicesSuravee Suthikulpanit
Add new GPIO device nodes and fix clock on gpio0. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Olof Johansson <olof@lixom.net>
generated by cgit v0.10.2 at 2024-07-25 13:49:20 (GMT)