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Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
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Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
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Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
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Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
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enable CONFIG_FSL_SDK_DPA instead of CONFIG_HAS_FSL_QBMAN
for 32b os on arm64
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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This patch adds SAI and eDMA support in the defconfig.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
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Add the memory free step to avoid the memory leak issue.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Add a "dump" interface to show the PCI transfer data.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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For more usability, instead of the the __get_free_pages with
dma_alloc_coherent to ensure the data's cache coherent from
PCI port to DDR memroy space.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Add a new input parameter for PCI-EP test to set the different
transfer data for each test time.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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The BARs has been set in u-boot, so in kernel
it does not need to be set again.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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There are different LUT offsets for different LS platforms.
Adding a private struct for each LS platform in the of_device_id
struct to bring in the specific LUT offset for the LS platform.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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The patch gets the MSI message address and data from MSI capability
and creates an outbound window to map MSI message address.
So writing data to this window will trigger a MSI interrupt.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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WARNING: drivers/built-in.o(.data+0x1024): Section mismatch in reference
from the variable ls_pcie_ep_driver to the function
.init.text:ls_pcie_ep_probe()
The variable ls_pcie_ep_driver references
the function __init ls_pcie_ep_probe()
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the
variable:
*_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console
drivers/built-in.o: In function `ls_pcie_ep_test_thread':
:(.text+0x1528a): undefined reference to `__aeabi_uldivmod'
:(.text+0x153a4): undefined reference to `__aeabi_uldivmod'
make: *** [vmlinux] Error 1
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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This driver is for Layerscape PCIe endpoint driver.
It provides "regs" "test" debug file operations.
"regs" read operation can dump the controller register;
writer can change register value.
"test" includes "init", "dma", "cpy", "free" commands which
are used to test DMA and memcpy EP performance.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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There is a mistake operation that select ARCH_DMA_ADDR_T_64BIT was taken
to error location. Now ARCH_DMA_ADDR_T_64BIT is unnecessary,
so it is removed.
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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fsl-mc works on IOVA addr if enabling smmu, otherwise it works on physics addr.
Add judgement of smmu status, dpaa2-qdma will disalbe
BMT bit in qdma-fd and qdma-list-table if enabling smmu.
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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Update qDMA driver to work with qDMA IP ver 1.1 from LS2 rev2.
The driver is still compatible with IP v1.0 from rev1.
Set the transaction type for command field for both source and
destination descriptors to coherent copy of cacheable memory.
Don't enable source prefetchable (SPF) in IP v1.0 FD since it
overlaps with IP v1.1 source read transaction QoS field.
Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com>
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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Update dpdmai command ids in order to work with MC 10.0.0.
The binary interface compatibility is maintained with MC v9.x.
Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com>
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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Support basic feature and scatter gather.
Up to 8 channels are supported.
Multi-threads per channel are supported.
Note:
For multi-threads per channel, the latter work may be completed first.
Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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LWC = 0b10: The last write is a posted write chased with a non-prefetchable
read. The read size is the same as last write when write size < 4B or
4B otherwise.
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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The qDMA completion queue has a Status Enqueue Required (SER) bit per
entry to indicate if a DMA job needs to enqueue over the QMan DCP
portal. This bit is first set when the completion queue entry is
allocated and the descriptor SER bit is also set. An entry is ready to
be enqueued when the DMA engine completes the DMA transfer for that job.
After a completion entry enqueues, the SER bit is cleared to indicate
that the entry can be removed which is done by shifting the queue. It is
possible that an earlier allocated entry is ready to shift (enqueued
previous cycle) while an entry is performing an enqueue
which requires clearing the SER bit next cycle. During the shift of the
queue, the SER bit is not cleared properly and will remain set which
causes an additional enqueue to occur for the same job.
Workaround: In the software, if the duplicate status notification is
seen, then discard it (calling “check duplicate status and discard” ).
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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ERR010812:
Enqueue rejection occurs as a results of the lack of processing by the
consumer of the command descriptors in the status queue. This may be due
to the size of the status queue, i.e. too small, to account for the
delay in reacting to an exceeded queue threshold or other means of
determining a non-empty status queue. While increasing the status queue
size may alleviate the occurrence of enqueue rejections, it is not a
complete solution. qDMA supports flow control (XOFF) flowing from the
status queue to the command queue(s) producing traffic. This flow
control is initiated when and enter XOFF watermark is triggered as
defined by register SQCCMR. Setting this to the recommended value in the
register description will guarantee that no enqueue rejections will ever
occur.
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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The patch is used for add the qdma command queue support.
Both qDMA source data and destination data can be either contiguous
or non-contiguous using one or more scatter/gather tables.
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
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Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
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Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
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Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
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This patch allows user-space to mmap PCI resources. This
patch is inline to arm32 bit implementation.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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QEIC was supported on PowerPC, and dependent on PPC,
Now it is supported on other platforms, so remove PPCisms.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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qeic_of_init just get device_node of qeic from dtb and call qe_ic_init,
pass the device_node to qe_ic_init.
So merge qeic_of_init into qe_ic_init to get the qeic node in
qe_ic_init.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/irq-qeic.c
For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);".
qe_ic_cascade_muxed_mpic was used for boards has the same interrupt
number for low interrupt and high interrupt, qe_ic_init has checked
if "low interrupt == high interrupt"
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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move the driver from drivers/soc/fsl/qe to drivers/irqchip,
merge qe_ic.h and qe_ic.c into irq-qeic.c.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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QE was supported on PowerPC, and dependent on PPC,
Now it is supported on other platforms. so remove PPCisms.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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1. modify bd_status from u32 to u16 in function hdlc_rx_done,
because bd_status register is 16bits
2. write bd_length register before writing bd_status register
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Numbering the ttyLPn space should not depend on the generic name
"serial<n>".
If don't add the alias node like:"serial0 = &lpuart0;", then lpuart
will probe failed:
[ 0.773410] fsl-lpuart 2950000.serial: failed to get alias id, errno -19
So remove the alias node dependence, and add the support for allocate the
line port automatically.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Sriram Dash <Sriram.dash@nxp.com>
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The console write code is not entirely race free (e.g. the operations
to disabling the UART interrupts are not atomic) hence locking is
required. This has been become apparent with the PREEMPT RT patchset
applied: With the fully preemptible kernel configuration the system
often ended up in a freeze already at startup.
Disable interrupts and lock using read_lock_irqsave. Try to lock in
the sysrq/oops case, but don't bother if locking fails.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Problem found via lockdep:
- lpuart_set_termios() calls del_timer_sync(&sport->lpuart_timer) while
holding sport->port.lock
- sport->lpuart_timer routine is lpuart_timer_func() that calls
lpuart_copy_rx_to_tty() that acquires same lock.
To fix, move Rx DMA stopping out of lock, as it already is in other places
in the same file.
While at it, also make Rx DMA start/stop code to look the same is in
other places in the same file.
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1
register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1)
for eSDHC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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Add device tree description info for Cortina 10G phy devices.
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Add basic support for Cortina PHY drivers. Support only CS4340 for now.
The phys are not compatible with IEEE 802.3 clause 22/45 registers.
Implement proper read_status support. The generic 10G phy driver causes
bus register access errors.
The driver should be described using the "ethernet-phy-id" device tree
compatible.
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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-revert define value change
Signed-off-by: costi <constantin.tudor@freescale.com>
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Signed-off-by: costi <constantin.tudor@freescale.com>
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