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2017-07-14arm64: dts: ls1012a: add the DTS node for QSPI supportAlison Wang
There is a s25fs512s qspi flash on QDS, RDB and FRDM board. Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
2017-07-14dts/ls1021a-twr: optimize fast-mode to quad modeYunhui Cui
The field "m25p,fast-read" means that flash works at fast-read mode. Now Quad read mode is supported, So we remove the field, and the quad read mode is enabled by default. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-07-14dts: ls1021a: Add the DTS for QSPI supportAlison Wang
This patch adds dts nodes for QSPI on LS1021A. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-07-14dts: ls1088a: add PCIe controller DT nodesHou Zhiqiang
LS1088a implements 3 PCIe 3.0 controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-07-14dts/ls1088a: add ranges to gic nodeZhao Qiang
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-07-14dts: ls2088a: add pcie supportHou Zhiqiang
The physical memory map address and CCSR registers map address are different between LS2088A and other LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-07-14arm64: dts: ls1046a: add PCIe controller DT nodesHou Zhiqiang
LS1046a implements 3 PCIe 3.0 controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-07-14arm64/dts-ls1043-ls2080: add pcie aer/pme interrupt-name property in the dtsPo Liu
Some platforms(NXP Layerscape for example) aer/pme interrupts was not MSI/MSI-X/INTx but using interrupt line independently. This patch add "aer", "pme" interrupt-names for aer/pme interrupt. With the interrupt-names "aer", "pme" code could probe aer/pme interrupt line for pcie root port, replace the aer/pme interrupt service irqs. This is intend to fixup the Layerscape platforms which aer/pmes interrupts was not MSI/MSI-X/INTx, but using interrupt line independently. Since the interrupt-names "intr" never been used. Remove it. Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-07-14arm/dts-ls1021: add pcie aer/pme interrupt-name property in the dtsPo Liu
NXP arm aer/pme interrupts was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" "pme" interrupt-names for aer/pme interrupts. With the interrupt-names "aer","pme" code could probe aer/pme interrupt line for pcie root port, replace the aer/pme interrupt service irqs. This patch is intend to fixup the Layerscape platforms which aer/pme interrupt was not MSI/MSI-X/INTx, but using interrupt line independently. Since the interrupt-names "intr" never been used. Remove it. Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-07-14ls1043ardb: add ds26522 node to dtsZhao Qiang
add ds26522 node to fsl-ls1043a-rdb.dts Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-07-14ls1043ardb: add qe node to ls1043ardbZhao Qiang
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-07-14arm64: dts: ls1088a: add fsl-mc hardware resource manager nodeLaurentiu Tudor
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2017-07-14arm64: dts: ls1088a: add gic its nodeLaurentiu Tudor
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
2017-07-14arm64: dts: add smmu device node in LS1088 devicetreeNipun Gupta
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
2017-07-14DT Binding: Comply with the new iommu binding for fsl_mcNipun Gupta
fsl-mc bus support the new iommu-map property. Comply to this binding for fsl_mc bus. Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
2017-07-14arm64: dts: ls1046a: add MSI dts nodeMinghuan Lian
LS1046a includes 3 MSI controllers. Each controller supports 128 interrupts. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-07-14arm64: dts: ls1043a: share all MSIsMinghuan Lian
In order to maximize the use of MSI, a PCIe controller will share all MSI controllers. The patch changes "msi-parent" to refer to all MSI controller dts nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-07-14arm: dts: ls1021a: share all MSIsMinghuan Lian
In order to maximize the use of MSI, a PCIe controller will share all MSI controllers. The patch changes msi-parent to refer to all MSI controller dts nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-07-14arm64: dts: ls1043a: fix typo of MSI compatible stringMinghuan Lian
"1" should be replaced by "l". This is a typo. The patch is to fix it. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-07-14arm: dts: ls1021a: fix typo of MSI compatible stringMinghuan Lian
"1" should be replaced by "l". This is a typo. The patch is to fix it. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-07-14arm64: dts: ls1012a: add eSDHC nodesyangbo lu
There are two eSDHC controllers in LS1012A. This patch is to add eSDHC nodes for ls1012a dts. Also enable eSDHC for RDB/QDS boards. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2017-07-14arm64: dts: ls208xa: support SD UHS-I on RDB and eMMC HS200 on QDSyangbo lu
This patch is to enable SD UHS-I mode on LS208xRDB and eMMC HS200 mode on LS208xQDS in dts. Also, the eSDHC peripheral clock must be used instead of platform clock to support these modes. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2017-07-14arm64: dts: ls1046a: support SD UHS-I and eMMC HS200 on RDByangbo lu
This patch is to enable SD UHS-I mode and eMMC HS200 mode on LS1046ARDB in dts. Also, the eSDHC peripheral clock must be used instead of platform clock to support these modes. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2017-07-14arm64: dts: freescale: update the copyright claimsLi Yang
Update the copyright claims to comply with company policy. Signed-off-by: Li Yang <leoyang.li@nxp.com>
2017-07-14arm64: dts: Add support for FSL's LS1088A SoCHarninder Rai
LS1088A contains eight ARM v8 CortexA53 processor cores with 32 KB L1-D cache and 32 KB L1-I cache Features summary Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs - Arranged as two clusters of four cores sharing a 1 MB L2 cache - Speed Up to 1.5 GHz - Support for cluster power-gating. Cache coherent interconnect (CCI-400) - Hardware-managed data coherency - Up to 700 MHz One 64-bit DDR4 SDRAM memory controller with ECC Data path acceleration architecture 2.0 (DPAA2) Three PCIe 3.0 controllers One serial ATA (SATA 3.0) controller Three high-speed USB 3.0 controllers with integrated PHY Following levels of DTSI/DTS files have been created for the LS1088A SoC family: - fsl-ls1088a.dtsi: DTS-Include file for NXP LS1088A SoC. - fsl-ls1088a-qds.dts: DTS file for NXP LS1088A QDS board. - fsl-ls1088a-rdb.dts: DTS file for NXP LS1088A RDB board Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>` Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: ls1012a: add crypto nodeHoria Geantă
LS1012A has a SEC v5.4 security engine. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: ls1012a: add thermal monitor nodeYuantian Tang
There is a thermal monitoring unit on ls1012a soc which can monitor and record the temperature of cores so that appropriate actions can be taken or alarm the user when the temperature exceeds a programmed temperature threshold. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: updated sata node on ls1012a platformYuantian Tang
Updated sata node to add ecc register address and dma coherence property. Enable sata on ls1012a platforms as well. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: added ecc register address to sata node on ls1046aTang Yuantian
For ls1046 sata, ecc should be disabled due to a erratum. Provide the ecc register address for driver to use. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: added ecc register address to sata node on ls1043aTang Yuantian
For ls1043 sata, ecc should be disabled due to a erratum. Provide the ecc register address for driver to use. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: freescale: ls2088a: Add DTS support for FSL's LS2088A SoCAbhimanyu Saini
This patch adds the device tree support for FSL LS2088A SoC based on ARMv8 architecture. Following levels of DTSI/DTS files have been created for the LS2088A SoC family: - fsl-ls2088a.dtsi: DTS-Include file for FSL LS2088A SoC. - fsl-ls2088a-qds.dts: DTS file for FSL LS2088A QDS board. - fsl-ls2088a-rdb.dts: DTS file for FSL LS2088A RDB board. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: freescale: ls2080a: Split devicetree for code resuabilityAbhimanyu Saini
LS2088A and LS2080A are similar SoCs with a few differences like ARM cores etc. Reorganize the LS2080A device tree to move the common nodes to: - fsl-ls208xa.dtsi - fsl-ls208xa-rdb.dtsi - fsl-ls208xa-qds.dtsi Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: ls1046a: Add TMU device tree supportJia Hongtao
Also add nodes and properties for thermal management support. Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: Add support for FSL's LS1012A SoCHarninder Rai
LS1012A features an advanced 64-bit ARM v8 CortexA53 processor with 32 KB of parity protected L1-I cache, 32 KB of ECC protected L1-D cache, as well as 256 KB of ECC protected L2 cache. Features summary One 64-bit ARM-v8 Cortex-A53 core with the following capabilities - Arranged as a cluster of one core supporting a 256 KB L2 cache with ECC protection - Speed up to 800 MHz - Parity-protected 32 KB L1 instruction cache and 32 KB L1 data cache - Neon SIMD engine - ARM v8 cryptography extensions One 16-bit DDR3L SDRAM memory controller ARM core-link CCI-400 cache coherent interconnect Cryptography acceleration (SEC) One Configurable x3 SerDes One PCI Express Gen2 controller, supporting x1 operation One serial ATA (SATA Gen 3.0) controller One USB 3.0/2.0 controller with integrated PHY Following levels of DTSI/DTS files have been created for the LS1012A SoC family: - fsl-ls1012a.dtsi: DTS-Include file for FSL LS1012A SoC. - fsl-ls1012a-frdm.dts: DTS file for FSL LS1012A FRDM board. - fsl-ls1012a-qds.dts: DTS file for FSL LS1012A QDS board. - fsl-ls1012a-rdb.dts: DTS file for FSL LS1012A RDB board. Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: ls2080a-rdb: remove disable status of pca9547Meng Yi
pca9547 won't probed since its status property is disabled. while there are devices connected to it, we need remove status property to let ds3232 and adt7461 probed correctly. Signed-off-by: Meng Yi <meng.yi@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14ARM64: dts: ls2080a: add device configuration nodeyangbo lu
Add the dts node for device configuration unit that provides general purpose configuration and status for the device. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Scott Wood <oss@buserror.net> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-07-14arm64: dts: ls2080a: Add TMU device tree support for LS2080AHongtao Jia
Also add nodes and properties for thermal management support. Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: ls1043a: Add TMU device tree support for LS1043AHongtao Jia
Also add nodes and properties for thermal management support. Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: add LS1046A-QDS board supportShaohui Xie
The LS1046A QorIQ development system (QDS) board is a high-performance computing, evaluation, development, and test platform supporting the LS1046A SoC. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: add LS1046A-RDB board supportMingkai Hu
The LS1046A reference design board (RDB) is a high-performance computing, evaluation, and development platform that supports the LS1046A SoC. Signed-off-by: Mingkai Hu <Mingkai.Hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14arm64: dts: add QorIQ LS1046A SoC supportMingkai Hu
LS1046A is an SoC with 4 ARMv8 A72 cores and most other IP blocks are similar to LS1043A which also complies to Freescale Chassis 2.1 spec. Created LS1046A SoC DTSI file to be included by board level DTS files. Signed-off-by: Horia Geant? <horia.geanta@nxp.com> Signed-off-by: Mihai Bantea <mihai.bantea@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boardsHarninder Rai
Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14dt-bindings: Add compatible for LS2088A QDS and RDB boardAbhimanyu Saini
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14Documentation: DT: add LS1012A compatible for SCFG and DCFGHarninder Rai
Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14Documentation: DT: Add entry for FSL LS1012A RDB, FRDM, QDS boardsHarninder Rai
Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14Documentation: DT: Add entry for QorIQ LS1046A-QDS boardShaohui Xie
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14Documentation: DT: Add entry for QorIQ LS1046A-RDB boardShaohui Xie
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFGShaohui Xie
SCFG and DCFG are SoC-specific devices can be found on SoCs like LS1021A, LS1043A and LS1046A, this patch updates bindings for SCFG and DCFG to reflect more SoCs. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible stringsShaohui Xie
Adds SoC compatible for LS1043A and LS2080A which are supported, and for LS1046A which is going to be supported. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-07-14config: arm64: open CONFIG_CLK_QORIQZhao Qiang
add CONFIG_CLK_QORIQ=y to arch/arm64/configs/defconfig Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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