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2017-09-25crypto: testmgr - avoid overlap in chunked testsArd Biesheuvel
The IDXn offsets are chosen such that tap values (which may go up to 255) end up overlapping in the xbuf allocation. In particular, IDX1 and IDX3 are too close together, so update IDX3 to avoid this issue. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - don't use stack buffer in test_acomp()Eric Biggers
With virtually-mapped stacks (CONFIG_VMAP_STACK=y), using the scatterlist crypto API with stack buffers is not allowed, and with appropriate debugging options will cause the 'BUG_ON(!virt_addr_valid(buf));' in sg_set_buf() to be triggered. Use a heap buffer instead. Fixes: d7db7a882deb ("crypto: acomp - update testmgr with support for acomp") Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - Do not test internal algorithmsHerbert Xu
Currently we manually filter out internal algorithms using a list in testmgr. This is dangerous as internal algorithms cannot be safely used even by testmgr. This patch ensures that they're never processed by testmgr at all. This patch also removes an obsolete bypass for nivciphers which no longer exist. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: acomp - update testmgr with support for acompGiovanni Cabiddu
Add tests to the test manager for algorithms exposed through acomp. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - add/enhance test cases for CRC-T10DIFArd Biesheuvel
The existing test cases only exercise a small slice of the various possible code paths through the x86 SSE/PCLMULQDQ implementation, and the upcoming ports of it for arm64. So add one that exceeds 256 bytes in size, and convert another to a chunked test. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: caam/qi - abort algorithm setup on DPAA2 partsHoria Geantă
caam/qi frontend (i.e. caamalg_qi) mustn't be used in case it runs on a DPAA2 part (this could happen when using a multiplatform kernel). Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-09-25crypto: caam/qi - don't include sg_sw_sec4.h headerHoria Geantă
sg_sw_sec4.h header is not used by caam/qi, thus remove its inclusion. This also solves the compilation failure due to name clashes between functions in sg_sw_qm.h and sg_sw_sec4.h -> sg_sw_qm2.h. Fixes: dd1bcf32df59 ("crypto: caam/jr - add support for DPAA2 parts") Reported-by: Radu Alexe <radu.alexe@nxp.com> Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-09-25crypto: caam/qi - explicitly set dma_opsHoria Geantă
Since ARM64 commit 1dccb598df549 ("arm64: simplify dma_get_ops"), dma_ops no longer default to swiotlb_dma_ops, but to dummy_dma_ops. We have to explicitly set dma_ops in the driver - at least for ARM64. Fixes: 67c2315def06 ("crypto: caam - add Queue Interface (QI) backend support") Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-09-25crypto: caam/qi - fix AD length endianness in S/G entryHoria Geantă
Associated data (AD) length is read by CAAM from an S/G entry that is initially filled by the GPP. Accordingly, AD length has to be stored in CAAM endianness. Fixes: b189817cf789 ("crypto: caam/qi - add ablkcipher and authenc algorithms") Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-09-25vfio fsl-mc: Map QBman cacheable region as cacheable non-shareableBharat Bhushan
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
2017-09-25vfio fsl-mc: Add read/write support for fsl-mc devicesBharat Bhushan
This patch adds support to read and write ioctls for fsl-mc devices. Only read-write to DPRC/DPMCP devices are supported while read writes on other fsl-mc devices is not supported by this patch. Also current patch limits userspace to write complete 64byte command once and read 64byte response by one ioctl. This will be reworked later to add support read/write to any offset Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
2017-09-25vfio fsl-mc: Reset container on _release()Bharat Bhushan
dprc_reset_container() does complete cleanup and thus allows re-run guest/user-space after abrupt guest kill. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
2017-09-25vfio fsl-mc: trigger an interrupt via eventfdBharat Bhushan
This patch allows to set an eventfd for fsl-mc device interrupt and also to trigger the interrupt eventfd from userspace for testing. All fsl-mc device interrupts are MSI type. This does not yet handler correctly DPRC container interrupt where re-scanning on container is required. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
2017-09-25vfio/fsl-mc: Add set_irq ioctl interface for fsl-mc devicesBharat Bhushan
This patch add interface of VFIO_DEVICE_SET_IRQS ioctl for fsl-mc devices. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
2017-09-25vfio/fsl-mc: Return get_irq info for fsl-mc deviceBharat Bhushan
This patch add support for VFIO_DEVICE_GET_IRQ_INFO for fsl-mc devices Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
2017-09-25vfio/fsl-mc: Allow userspace to MMAP fsl-mc device MMIO regionsBharat Bhushan
Allow userspace to mmap device regions for direct access of fsl-mc devices. QBman CENA registers are cacheable and non-shareable but map CENA region (marked as REGION_TYPE_CACHEABLE) to be the non-cacheable to avoid coherency issues if a user migrates to another core. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
2017-09-25vfio fsl-mc: Return fsl-mc device MMIO region infoBharat Bhushan
Add support for VFIO_DEVICE_GET_REGION_INFO ioctl call. This allows usespace to know device mmap-able region details. MC device (DPIO) have a region which is cacheable and non-shareable. Describe these regions as cacheable so that during mmap() they will be mapped accordingly. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
2017-09-25vfio/fsl-mc: Return fsl-mc device infoBharat Bhushan
Allow userspace to get fsl-mc device info by making VFIO_DEVICE_GET_INFO ioctl. With this usespace will get basic device info such as number of regions and irqs. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
2017-09-25vfio/fsl-mc: Add vfio-fsl-mc in Makefile and KconfigBharat Bhushan
commit 7a3d5ea46413924daefb7d4af24d04d7c5f54b98 [context adjustment] Enable building vfio FSL-MC driver to allow FSL-MC devices binding with VFIO. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25vfio/fsl-mc: non-dprc device support addedBharat Bhushan
Non-DPRC devices shares it's parent container MC portal to communicate to MC hardware. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
2017-09-25vfio/fsl-mc: Initialize and scan dprc container on driver bindBharat Bhushan
DPRC (Data Path Resource Container) device is a bus devices and have child devices within it. This patch add support for initializing and scanning the DPRC container. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
2017-09-25vfio/fsl-mc: Add VFIO framework for fsl-mc devicesBharat Bhushan
commit f8adf3ce07cf0623b3e8e0df67f3bc12a110416f [context adjustment] This patch add framework of VFIO support for FSL-MC devices. Subsequent patches will add support for binding and secure assigning these devices using VFIO. FSL-MC is a new bus (driver/bus/fsl-mc/) which is different from PCI and Platform bus. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25iommu: arm-smmu: Add support for the fsl-mc busNipun Gupta
Implement bus specific support for the fsl-mc bus including registering the arm_smmu_ops and bus specific device add operations. Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
2017-09-25iommu/arm-smmu: Return IOVA in iova_to_phys when SMMU is bypassedSunil Goutham
For software initiated address translation, when domain type is IOMMU_DOMAIN_IDENTITY i.e SMMU is bypassed, mimic HW behavior i.e return the same IOVA as translated address. This patch is an extension to Will Deacon's patchset "Implement SMMU passthrough using the default domain". Signed-off-by: Sunil Goutham <sgoutham@cavium.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-09-25net: phy: add SGMII 2500 PHYMadalin Bucur
Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
2017-09-25drivers: phy: Add Freescale backplane phy driverBogdan Purcareata
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
2017-09-25net: phy: Check phydev->drvFlorian Fainelli
There are number of function calls, originating from user-space, typically through the Ethernet driver that can make us crash by dereferencing phydev->drv which will be NULL once we unbind the driver from the PHY. There are still functional issues that prevent an unbind then rebind to work, but these will be addressed separately. Suggested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-09-25mtd: fsl-quadspi: add u32 to u8 transform functionAlison Wang
The TX/RX Buffer Data Register in QSPI is 32-bit register. So the 32bit data need transform to 4bytes data. But the "*((u32 *)rxbuf) = tmp" will depend on endian of the core. We add endian independence function to do the 32bit data to 4bytes transition. Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
2017-09-25mtd: spi-nor: disable 4kb sector erase for s25fl128Suresh Gupta
As for s25fl128s flash, the sectors are organized either as a hybrid combination of 4-kB and 64-kB sectors, or as uniform 256-kbyte sectors. we should use the command 0xd8 to erase all bits, not the Parameter 4-kB Sector Erase (P4E) command 0x20. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd: spi-nor: add DDR quad read supportAlison Wang
This patch adds the DDR quad read support by the following: [1] add SPI_NOR_DDR_QUAD read mode. [2] add DDR Quad read opcodes: SPINOR_OP_READ_1_4_4_D / SPINOR_OP_READ4_1_4_4_D [3] add set_ddr_quad_mode() to initialize for the DDR quad read. Currently it only works for Spansion NOR. [4] set dummy with 6 for Spansion family Test this patch for Spansion s25fl128s NOR flash. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd: spi-nor: Support R/W for S25FS-S family flashAlison Wang
With the physical sectors combination, S25FS-S family flash requires some special operations for read/write functions. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd:spi_nor: Disable Micron flash HW protectionSuresh Gupta
For Micron family ,The status register write enable/disable bit, provides hardware data protection for the device When the enable/disable bit is set to 1, the status register nonvolatile bits become read-only and the WRITE STATUS REGISTER operation will not execute. Signed-off-by: Yunhui Cui <B56489@freescale.com>
2017-09-25mtd: spi-nor: Add support for N25Q256A11Nobuhiro Iwamatsu
Add new Micron N25Q256A (N25Q256A11) 256Mbit NOR Flash in the list of supported devices. This chip has the same structure as the N25Q256A but ID and voltage (1V8) to use is different. Therefore, this adds N25Q256A11 as n25q256ax1. In the future, for new Micron memories we could use the patterns "n25q*ax1" for 1V8 and "n25q*ax3" for 3V3 memories. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25drivers mtd: spi-nor: add Macronix MX25Ux033E and MX25Ux035 variantsAlexander Kurz
Macronix MX25U2033E, MX25U4033E and MX25U4035 devices are used in 4/5/6th generation Kindle ebook readers. Both MX25U403x variants share the same JEDEC id. Add those spi-nor variants and the similar MX25U8035 mentioned in the same set of datasheets. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25drivers mtd: spi-nor: add Winbond W25Q20 variantsAlexander Kurz
Winbond W25Q20BW devices are used in 4/5th generation Kindle ebook readers. Add this spi-nor device and the similar W25Q20 devices to the list of known devices. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Disable chip erase for Micron n25q00.mar.krzeminski
Micron n25q00 are stacked chips, thus do not support chip erase. >From now spi-nor framework will not send chip erase command, instead will use sector at time erase procedure. Signed-off-by: Marcin Krzeminski <mar.krzeminski@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Fix whole chip erasing for stacked chips.mar.krzeminski
Currently it is possible to disable chip erase for spi-nor driver. Some modern stacked (multi die) flash chips do not support chip erase opcode at all but spi-nor framework needs to cope with them too. This commit extends existing functionality to allow disable chip erase for a single flash chip. Signed-off-by: Marcin Krzeminski <mar.krzeminski@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Add support for ESMT F25L32QA and F25L64QAL. D. Pinney
Add support for the ESMT F25L32QA and F25L64QA. These are 4MB and 8MB SPI-NOR Chips from Elite Semiconductor Memory Technology. Signed-off-by: L. D. Pinney <ldpinney@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Add support for gd25q16Kamal Dasu
Add GigaDevice GD25Q16 (16M-bit) to supported list. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Fix S3AN addressing calculationRicardo Ribalda
The page calculation under spi_nor_s3an_addr_convert() was wrong. On Default Address Mode we need to perform a divide by page_size. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Add lock/unlock support for f25l32paVictor Shyba
This chip has write protection enabled on power-up, so this flag is necessary to support write operations. Signed-off-by: Victor Shyba <victor1984@riseup.net> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: add a stateless method to support memory size above 128MibCyrille Pitchen
This patch provides an alternative mean to support memory above 16MiB (128Mib) by replacing 3byte address op codes by their associated 4byte address versions. Using the dedicated 4byte address op codes doesn't change the internal state of the SPI NOR memory as opposed to using other means such as updating a Base Address Register (BAR) and sending command to enter/leave the 4byte mode. Hence when a CPU reset occurs, early bootloaders don't need to be aware of BAR value or 4byte mode being enabled: they can still access the first 16MiB of the SPI NOR memory using the regular 3byte address op codes. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Tested-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2017-09-25mtd: spi-nor: rename SPINOR_OP_* macros of the 4-byte address op codesAlison Wang
This patch renames the SPINOR_OP_* macros of the 4-byte address instruction set so the new names all share a common pattern: the 4-byte address name is built from the 3-byte address name appending the "_4B" suffix. The patch also introduces new op codes to support other SPI protocols such as SPI 1-4-4 and SPI 1-2-2. This is a transitional patch and will help a later patch of spi-nor.c to automate the translation from the 3-byte address op codes into their 4-byte address version. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2017-09-25mtd: spi-nor: remove WARN_ONCE() message in spi_nor_write()Cyrille Pitchen
This patch removes the WARN_ONCE() test in spi_nor_write(). This macro triggers the display of a warning message almost every time we use a UBI file-system because a write operation is performed at offset 64, which is in the middle of the SPI NOR memory page. This is a valid operation for ubifs. Hence this warning is pretty annoying and useless so we just remove it. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Suggested-by: Richard Weinberger <richard@nod.at> Suggested-by: Andras Szemzo <szemzo.andras@gmail.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2017-09-25mtd: spi-nor: improve macronix_quad_enable()Cyrille Pitchen
The patch checks whether the Quad Enable bit is already set in the Status Register. If so, the function exits immediately with a successful return code. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2017-09-25spi-nor: Add support for S3AN spi-nor devicesAlison Wang
Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep their configuration data and (optionally) some user data. The protocol of this flash follows most of the spi-nor standard. With the following differences: - Page size might not be a power of two. - The address calculation (default addressing mode). - The spi nor commands used. Protocol is described on Xilinx User Guide UG333 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: Fix typo: "occured" -> "occurred"Nobuhiro Iwamatsu
Trivial typo fix in comment. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2017-09-25mtd: spi-nor: Add support for mr25h40IWAMOTO Masahiko
Add Everspin mr25h40 512KB MRAM to the list of supported chips. Signed-off-by: Masahiko Iwamoto <iwamoto@allied-telesis.co.jp> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Add support for N25Q016AMoritz Fischer
This commit adds support in the spi-nor driver for the N25Q016A, a 16Mbit SPI NOR flash from Micron. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Jagan Teki <jteki@openedev.com> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Add at25df321 spi-nor flash supportJagan Teki
Add Atmel at25df321 spi-nor flash to the list of spi_nor_ids. Cc: Brian Norris <computersforpeace@gmail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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