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2017-09-25irqchip/qeic: merge qeic init code from platforms to a common functionZhao Qiang
The codes of qe_ic init from a variety of platforms are redundant, merge them to a common function and put it to irqchip/irq-qeic.c For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0, qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of "qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);". qe_ic_cascade_muxed_mpic was used for boards has the same interrupt number for low interrupt and high interrupt, qe_ic_init has checked if "low interrupt == high interrupt" Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25irqchip/qeic: move qeic driver from drivers/soc/fsl/qeZhao Qiang
move the driver from drivers/soc/fsl/qe to drivers/irqchip, merge qe_ic.h and qe_ic.c into irq-qeic.c. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25QE: remove PPCisms for QEZhao Qiang
QE was supported on PowerPC, and dependent on PPC, Now it is supported on other platforms. so remove PPCisms. Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25ucc/hdlc: fix two little issueZhao Qiang
1. modify bd_status from u32 to u16 in function hdlc_rx_done, because bd_status register is 16bits 2. write bd_length register before writing bd_status register Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-09-25serial: fsl_lpuart: Remove the alias node dependenceYuan Yao
Numbering the ttyLPn space should not depend on the generic name "serial<n>". If don't add the alias node like:"serial0 = &lpuart0;", then lpuart will probe failed: [ 0.773410] fsl-lpuart 2950000.serial: failed to get alias id, errno -19 So remove the alias node dependence, and add the support for allocate the line port automatically. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Sriram Dash <Sriram.dash@nxp.com>
2017-09-25tty: serial: fsl_lpuart: lock port on console writeStefan Agner
The console write code is not entirely race free (e.g. the operations to disabling the UART interrupts are not atomic) hence locking is required. This has been become apparent with the PREEMPT RT patchset applied: With the fully preemptible kernel configuration the system often ended up in a freeze already at startup. Disable interrupts and lock using read_lock_irqsave. Try to lock in the sysrq/oops case, but don't bother if locking fails. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-09-25tty: serial: fsl_lpuart: fix del_timer_sync() vs timer routine deadlockNikita Yushchenko
Problem found via lockdep: - lpuart_set_termios() calls del_timer_sync(&sport->lpuart_timer) while holding sport->port.lock - sport->lpuart_timer routine is lpuart_timer_func() that calls lpuart_copy_rx_to_tty() that acquires same lock. To fix, move Rx DMA stopping out of lock, as it already is in other places in the same file. While at it, also make Rx DMA start/stop code to look the same is in other places in the same file. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Tested-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-09-25mmc: sdhci-of-esdhc: support ESDHC_CAPABILITIES_1 accessingYangbo Lu
eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1 register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1) for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2017-09-25dt-bindings: net: Add Cortina device tree bindingsBogdan Purcareata
Add device tree description info for Cortina 10G phy devices. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-09-25net: phy: Add Cortina CS4340 driverBogdan Purcareata
Add basic support for Cortina PHY drivers. Support only CS4340 for now. The phys are not compatible with IEEE 802.3 clause 22/45 registers. Implement proper read_status support. The generic 10G phy driver causes bus register access errors. The driver should be described using the "ethernet-phy-id" device tree compatible. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-09-25fsl-backplane: Get backplane link status from pcscosti
-revert define value change Signed-off-by: costi <constantin.tudor@freescale.com>
2017-09-25fsl-backplane: Access SerDes regs as LEcosti
Signed-off-by: costi <constantin.tudor@freescale.com>
2017-09-25mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handlingYangbo Lu
SD controller with SDHCI_QUIRK_NO_HISPD_BIT quirk probably use high speed enable bit for other purpose. So this bit shouldn't be changed for high speed enabling for this type of SD controller. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2017-09-25mmc: sdhci: put together into one condition checkingJaehoon Chung
value of ios->timing is not related with SDCHI v3.0. If Controller version is v3.0, SDHCI_QUIRK_NO_HISPD_BIT is meaningless. To prevent the setting wrong bit moves into one condition checking. (e.g sdhci-s3c doesn't use SDHCI_CTRL_HISPD bit, instead using this bit as other purpose.) Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2017-09-25staging: fsl-dpaa2/eth: Set Tx timestamp support correctlyIoana Radulescu
We used to set pass_timestamp parameter only for Tx confirmation buffer layout config, when in fact MC also looks at the Tx buffer layout when deciding whether to enable Tx timestamping support or not. Older versions of MC (< MC.1.x) enabled this support regardless of user config, so the issue was hidden. Copy the pass_timestamp setting to Tx buffer layout configuration. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
2017-09-25staging: fsl-dpaa2/eth: Fix access to CSCN memoryIoana Radulescu
Make sure the memory area where the hardware writes the congestion state is properly synchronized before reading it. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
2017-09-25staging: fsl-dpaa2/eth: Fix NULL pointer accessIoana Radulescu
If build_frag_skb() fails, we risk accessing the skb pointer before checking it's not NULL. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
2017-09-25staging: fsl-dpaa2/eth: Fix adding FS rule at specific locationIoana Radulescu
When inserting a flow steering rule through ethtool, the user may specify a location index. Ethtool manual says the expected behaviour is to overwrite any rule present in that location. What currently happens is that the driver passes on the location to MC with no further verifications and if there's already a rule present at that index, MC returns an error. Fix this by making sure the location is available, and if not free the current entry before inserting the new one. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
2017-09-25staging: fsl-dpaa2/eth: Fix skb use after freeBogdan Purcareata
Once a Tx frame descriptor is enqueued, an interrupt might be triggered to process the Tx confirmation and free the skb, hitting a memory use after free when updating the tx_bytes statistic based on skb->len. Use the frame descriptor length instead. Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
2017-09-25staging: fsl-dpaa2/eth: Fix use of uninitialized priv fieldsIoana Radulescu
Private structure fields "hash_fields" and "num_hash_fields" were used in check_cls_support() even though they were initialized later. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
2017-09-25Added missing fields to dprc_rsp_get_obj_region structureCristian Sovaiala
'type' and 'flags' fields were missing from dprc_rsp_get_obj_region structure therefore the MC Bus driver was not receiving proper flags from MC like DPRC_REGION_CACHEABLE. Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
2017-09-25usb: dwc3 : Add support for USB snoopingRajesh Bhagat
Add support for USB3 snooping by asserting bits in register DWC3_GSBUSCFG0 for data and descriptor Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
2017-09-25usb: dts: for fix usb port faile issue on ls1021atwryinbo.zhu
Signed-off-by: yinbo zhu <yinbo.zhu@nxp.com>
2017-09-25arm: dts: Add big-endian for IFC on LS1021AAlison Wang
For the patch to update struct map_info's swap field based on device characteristics defined in device tree, big-endian parameter is added for LS1021A. Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-09-25armv8: dts: Add big-endian for IFC on LS1043A/LS1046AAlison Wang
For the patch to update struct map_info's swap field based on device characteristics defined in device tree, big-endian parameter is added for LS1043A/LS1046A. Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-09-25driver: mtd: update struct map_info's swap as per map requirementAlison Wang
It is not necessary for all device's maps to be CFI_HOST_ENDIAN. Maps device can be big endian or little endian. Currently it is being taken care using CONFIG_MTD_CFI_LE_BYTE_SWAP or CONFIG_MTD_CFI_BE_BYTE_SWAP i.e. compile time. Now update struct map_info's swap field based on device characteristics defined in device tree. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-09-25driver: mtd: ifc: update bufnum mask for ver >= 2.0.0Prabhakar Kushwaha
Bufnum mask is used to calculate page position in the internal SRAM. As IFC version 2.0.0 has 16KB of internal SRAM as compared to older versions which had 8KB. Hence bufnum mask needs to be updated. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-09-25driver: mtd: ifc: Initialize SRAM for all version >= 1.0Alison Wang
All IFC version >= 1.0 use 28nm technology for SRAM. Here SRAM has a requirement to initialize before any read operation performed for avoiding ECC Error. So update condition check to initialize SRAM for all IFC version >= 1.0.0. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2017-09-25mtd: spi-nor: Fix the wrong setting for SPI_NOR_DDR_QUAD_READAlison Wang
SPI_NOR_DDR_QUAD_READ is set to the wrong number. This patch will fix the bug and set SPI_NOR_DDR_QUAD_READ to the correct number. Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-09-25crypto: acomp - add driver-side scomp interfaceGiovanni Cabiddu
Add a synchronous back-end (scomp) to acomp. This allows to easily expose the already present compression algorithms in LKCF via acomp. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: acomp - add asynchronous compression apiGiovanni Cabiddu
Add acomp, an asynchronous compression api that uses scatterlist buffers. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: caam - fix signals handlingHoria Geantă
Driver does not properly handle the case when signals interrupt wait_for_completion_interruptible(): -it does not check for return value -completion structure is allocated on stack; in case a signal interrupts the sleep, it will go out of scope, causing the worker thread (caam_jr_dequeue) to fail when it accesses it wait_for_completion_interruptible() is replaced with uninterruptable wait_for_completion(). We choose to block all signals while waiting for I/O (device executing the split key generation job descriptor) since the alternative - in order to have a deterministic device state - would be to flush the job ring (aborting *all* in-progress jobs). Cc: <stable@vger.kernel.org> Fixes: 045e36780f115 ("crypto: caam - ahash hmac support") Fixes: 4c1ec1f930154 ("crypto: caam - refactor key_gen, sg") Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au> (cherry picked from commit 7459e1d25ffefa2b1be799477fcc1f6c62f6cec7)
2017-09-25crypto: caam/qi2 - add support for TLS 1.0 recordRadu Alexe
TLS 1.0 descriptors run on SEC 4.x or higher. For now, only tls10(hmac(sha1),cbc(aes)) algorithm is registered by the driver. Known limitations: - when src == dst - there should be no element in the src scatterlist array that contains both associated data and message data. - when src != dst - associated data is not copied from source into destination. - for decryption when src != dst the size of the destination should be large enough so that the buffer may contain the decrypted authenc and padded data. Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
2017-09-25crypto: caam/qi - add support for TLS 1.0 recordRadu Alexe
TLS 1.0 descriptors run on SEC 4.x or higher. For now, only tls10(hmac(sha1),cbc(aes)) algorithm is registered by the driver. Known limitations: - when src == dst - there should be no element in the src scatterlist array that contains both associated data and message data. - when src != dst - associated data is not copied from source into destination. - for decryption when src != dst the size of the destination should be large enough so that the buffer may contain the decrypted authenc and padded data. Signed-off-by: Tudor Ambarus <tudor-dan.ambarus@nxp.com> Signed-off-by: Cristian Stoica <cristian.stoica@nxp.com> Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
2017-09-25crypto: caam - add support for MOVEB commandRadu Alexe
CHAs of SEC work natively in BE mode. When moving data to the alignment blocks, swapping is needed for LE platforms. This is done by means of the MOVEB command. This patch adds support to DCL for this command. Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com> Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
2017-09-25crypto: add support for TLS 1.0 record encryptionRadu Alexe
This patch adds kernel support for encryption/decryption of TLS 1.0 records using block ciphers. Implementation is similar to authenc in the sense that the base algorithms (AES, SHA1) are combined in a template to produce TLS encapsulation frames. The composite algorithm will be called "tls10(hmac(<digest>),cbc(<cipher>))". The cipher and hmac keys are wrapped in the same format used by authenc.c. Signed-off-by: Radu Alexe <radu.alexe@nxp.com> Signed-off-by: Cristian Stoica <cristian.stoica@nxp.com> Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-09-25crypto: testmgr - mark ctr(des3_ede) as fips_allowedMarcelo Cerri
3DES is missing the fips_allowed flag for CTR mode. Signed-off-by: Marcelo Henrique Cerri <marcelo.cerri@canonical.com> Acked-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - constify all test vectorsEric Biggers
Cryptographic test vectors should never be modified, so constify them to enforce this at both compile-time and run-time. This moves a significant amount of data from .data to .rodata when the crypto tests are enabled. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - add test cases for cbcmac(aes)Ard Biesheuvel
In preparation of splitting off the CBC-MAC transform in the CCM driver into a separate algorithm, define some test cases for the AES incarnation of cbcmac. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - use calculated count for number of test vectorsArd Biesheuvel
When working on AES in CCM mode for ARM, my code passed the internal tcrypt test before I had even bothered to implement the AES-192 and AES-256 code paths, which is strange because the tcrypt does contain AES-192 and AES-256 test vectors for CCM. As it turned out, the define AES_CCM_ENC_TEST_VECTORS was out of sync with the actual number of test vectors, causing only the AES-128 ones to be executed. So get rid of the defines, and wrap the test vector references in a macro that calculates the number of vectors automatically. The following test vector counts were out of sync with the respective defines: BF_CTR_ENC_TEST_VECTORS 2 -> 3 BF_CTR_DEC_TEST_VECTORS 2 -> 3 TF_CTR_ENC_TEST_VECTORS 2 -> 3 TF_CTR_DEC_TEST_VECTORS 2 -> 3 SERPENT_CTR_ENC_TEST_VECTORS 2 -> 3 SERPENT_CTR_DEC_TEST_VECTORS 2 -> 3 AES_CCM_ENC_TEST_VECTORS 8 -> 14 AES_CCM_DEC_TEST_VECTORS 7 -> 17 AES_CCM_4309_ENC_TEST_VECTORS 7 -> 23 AES_CCM_4309_DEC_TEST_VECTORS 10 -> 23 CAMELLIA_CTR_ENC_TEST_VECTORS 2 -> 3 CAMELLIA_CTR_DEC_TEST_VECTORS 2 -> 3 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - Allocate only the required output size for hash testsAndrew Lutomirski
There are some hashes (e.g. sha224) that have some internal trickery to make sure that only the correct number of output bytes are generated. If something goes wrong, they could potentially overrun the output buffer. Make the test more robust by allocating only enough space for the correct output size so that memory debugging will catch the error if the output is overrun. Tested by intentionally breaking sha224 to output all 256 internally-generated bits while running on KASAN. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Herbert Xu <herbert@gondor.apana.org.au> Signed-off-by: Andy Lutomirski <luto@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - use kmemdup instead of kmalloc+memcpyEric Biggers
It's recommended to use kmemdup instead of kmalloc followed by memcpy. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - Use heap buffer for acomp test inputLaura Abbott
Christopher Covington reported a crash on aarch64 on recent Fedora kernels: kernel BUG at ./include/linux/scatterlist.h:140! Internal error: Oops - BUG: 0 [#1] PREEMPT SMP Modules linked in: CPU: 2 PID: 752 Comm: cryptomgr_test Not tainted 4.9.0-11815-ge93b1cc #162 Hardware name: linux,dummy-virt (DT) task: ffff80007c650080 task.stack: ffff800008910000 PC is at sg_init_one+0xa0/0xb8 LR is at sg_init_one+0x24/0xb8 ... [<ffff000008398db8>] sg_init_one+0xa0/0xb8 [<ffff000008350a44>] test_acomp+0x10c/0x438 [<ffff000008350e20>] alg_test_comp+0xb0/0x118 [<ffff00000834f28c>] alg_test+0x17c/0x2f0 [<ffff00000834c6a4>] cryptomgr_test+0x44/0x50 [<ffff0000080dac70>] kthread+0xf8/0x128 [<ffff000008082ec0>] ret_from_fork+0x10/0x50 The test vectors used for input are part of the kernel image. These inputs are passed as a buffer to sg_init_one which eventually blows up with BUG_ON(!virt_addr_valid(buf)). On arm64, virt_addr_valid returns false for the kernel image since virt_to_page will not return the correct page. Fix this by copying the input vectors to heap buffer before setting up the scatterlist. Reported-by: Christopher Covington <cov@codeaurora.org> Fixes: d7db7a882deb ("crypto: acomp - update testmgr with support for acomp") Signed-off-by: Laura Abbott <labbott@redhat.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - fix overlap in chunked tests againArd Biesheuvel
Commit 7e4c7f17cde2 ("crypto: testmgr - avoid overlap in chunked tests") attempted to address a problem in the crypto testmgr code where chunked test cases are copied to memory in a way that results in overlap. However, the fix recreated the exact same issue for other chunked tests, by putting IDX3 within 492 bytes of IDX1, which causes overlap if the first chunk exceeds 492 bytes, which is the case for at least one of the xts(aes) test cases. So increase IDX3 by another 1000 bytes. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - avoid overlap in chunked testsArd Biesheuvel
The IDXn offsets are chosen such that tap values (which may go up to 255) end up overlapping in the xbuf allocation. In particular, IDX1 and IDX3 are too close together, so update IDX3 to avoid this issue. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - don't use stack buffer in test_acomp()Eric Biggers
With virtually-mapped stacks (CONFIG_VMAP_STACK=y), using the scatterlist crypto API with stack buffers is not allowed, and with appropriate debugging options will cause the 'BUG_ON(!virt_addr_valid(buf));' in sg_set_buf() to be triggered. Use a heap buffer instead. Fixes: d7db7a882deb ("crypto: acomp - update testmgr with support for acomp") Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - Do not test internal algorithmsHerbert Xu
Currently we manually filter out internal algorithms using a list in testmgr. This is dangerous as internal algorithms cannot be safely used even by testmgr. This patch ensures that they're never processed by testmgr at all. This patch also removes an obsolete bypass for nivciphers which no longer exist. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: acomp - update testmgr with support for acompGiovanni Cabiddu
Add tests to the test manager for algorithms exposed through acomp. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: testmgr - add/enhance test cases for CRC-T10DIFArd Biesheuvel
The existing test cases only exercise a small slice of the various possible code paths through the x86 SSE/PCLMULQDQ implementation, and the upcoming ports of it for arm64. So add one that exceeds 256 bytes in size, and convert another to a chunked test. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-09-25crypto: caam/qi - abort algorithm setup on DPAA2 partsHoria Geantă
caam/qi frontend (i.e. caamalg_qi) mustn't be used in case it runs on a DPAA2 part (this could happen when using a multiplatform kernel). Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
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