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2017-09-25vfio/fsl-mc: Add VFIO framework for fsl-mc devicesBharat Bhushan
commit f8adf3ce07cf0623b3e8e0df67f3bc12a110416f [context adjustment] This patch add framework of VFIO support for FSL-MC devices. Subsequent patches will add support for binding and secure assigning these devices using VFIO. FSL-MC is a new bus (driver/bus/fsl-mc/) which is different from PCI and Platform bus. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25iommu: arm-smmu: Add support for the fsl-mc busNipun Gupta
Implement bus specific support for the fsl-mc bus including registering the arm_smmu_ops and bus specific device add operations. Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
2017-09-25iommu/arm-smmu: Return IOVA in iova_to_phys when SMMU is bypassedSunil Goutham
For software initiated address translation, when domain type is IOMMU_DOMAIN_IDENTITY i.e SMMU is bypassed, mimic HW behavior i.e return the same IOVA as translated address. This patch is an extension to Will Deacon's patchset "Implement SMMU passthrough using the default domain". Signed-off-by: Sunil Goutham <sgoutham@cavium.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-09-25net: phy: add SGMII 2500 PHYMadalin Bucur
Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
2017-09-25drivers: phy: Add Freescale backplane phy driverBogdan Purcareata
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
2017-09-25net: phy: Check phydev->drvFlorian Fainelli
There are number of function calls, originating from user-space, typically through the Ethernet driver that can make us crash by dereferencing phydev->drv which will be NULL once we unbind the driver from the PHY. There are still functional issues that prevent an unbind then rebind to work, but these will be addressed separately. Suggested-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2017-09-25mtd: fsl-quadspi: add u32 to u8 transform functionAlison Wang
The TX/RX Buffer Data Register in QSPI is 32-bit register. So the 32bit data need transform to 4bytes data. But the "*((u32 *)rxbuf) = tmp" will depend on endian of the core. We add endian independence function to do the 32bit data to 4bytes transition. Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
2017-09-25mtd: spi-nor: disable 4kb sector erase for s25fl128Suresh Gupta
As for s25fl128s flash, the sectors are organized either as a hybrid combination of 4-kB and 64-kB sectors, or as uniform 256-kbyte sectors. we should use the command 0xd8 to erase all bits, not the Parameter 4-kB Sector Erase (P4E) command 0x20. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd: spi-nor: add DDR quad read supportAlison Wang
This patch adds the DDR quad read support by the following: [1] add SPI_NOR_DDR_QUAD read mode. [2] add DDR Quad read opcodes: SPINOR_OP_READ_1_4_4_D / SPINOR_OP_READ4_1_4_4_D [3] add set_ddr_quad_mode() to initialize for the DDR quad read. Currently it only works for Spansion NOR. [4] set dummy with 6 for Spansion family Test this patch for Spansion s25fl128s NOR flash. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd: spi-nor: Support R/W for S25FS-S family flashAlison Wang
With the physical sectors combination, S25FS-S family flash requires some special operations for read/write functions. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd:spi_nor: Disable Micron flash HW protectionSuresh Gupta
For Micron family ,The status register write enable/disable bit, provides hardware data protection for the device When the enable/disable bit is set to 1, the status register nonvolatile bits become read-only and the WRITE STATUS REGISTER operation will not execute. Signed-off-by: Yunhui Cui <B56489@freescale.com>
2017-09-25mtd: spi-nor: Add support for N25Q256A11Nobuhiro Iwamatsu
Add new Micron N25Q256A (N25Q256A11) 256Mbit NOR Flash in the list of supported devices. This chip has the same structure as the N25Q256A but ID and voltage (1V8) to use is different. Therefore, this adds N25Q256A11 as n25q256ax1. In the future, for new Micron memories we could use the patterns "n25q*ax1" for 1V8 and "n25q*ax3" for 3V3 memories. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25drivers mtd: spi-nor: add Macronix MX25Ux033E and MX25Ux035 variantsAlexander Kurz
Macronix MX25U2033E, MX25U4033E and MX25U4035 devices are used in 4/5/6th generation Kindle ebook readers. Both MX25U403x variants share the same JEDEC id. Add those spi-nor variants and the similar MX25U8035 mentioned in the same set of datasheets. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25drivers mtd: spi-nor: add Winbond W25Q20 variantsAlexander Kurz
Winbond W25Q20BW devices are used in 4/5th generation Kindle ebook readers. Add this spi-nor device and the similar W25Q20 devices to the list of known devices. Signed-off-by: Alexander Kurz <akurz@blala.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Disable chip erase for Micron n25q00.mar.krzeminski
Micron n25q00 are stacked chips, thus do not support chip erase. >From now spi-nor framework will not send chip erase command, instead will use sector at time erase procedure. Signed-off-by: Marcin Krzeminski <mar.krzeminski@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Fix whole chip erasing for stacked chips.mar.krzeminski
Currently it is possible to disable chip erase for spi-nor driver. Some modern stacked (multi die) flash chips do not support chip erase opcode at all but spi-nor framework needs to cope with them too. This commit extends existing functionality to allow disable chip erase for a single flash chip. Signed-off-by: Marcin Krzeminski <mar.krzeminski@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Add support for ESMT F25L32QA and F25L64QAL. D. Pinney
Add support for the ESMT F25L32QA and F25L64QA. These are 4MB and 8MB SPI-NOR Chips from Elite Semiconductor Memory Technology. Signed-off-by: L. D. Pinney <ldpinney@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Add support for gd25q16Kamal Dasu
Add GigaDevice GD25Q16 (16M-bit) to supported list. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Fix S3AN addressing calculationRicardo Ribalda
The page calculation under spi_nor_s3an_addr_convert() was wrong. On Default Address Mode we need to perform a divide by page_size. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Add lock/unlock support for f25l32paVictor Shyba
This chip has write protection enabled on power-up, so this flag is necessary to support write operations. Signed-off-by: Victor Shyba <victor1984@riseup.net> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: add a stateless method to support memory size above 128MibCyrille Pitchen
This patch provides an alternative mean to support memory above 16MiB (128Mib) by replacing 3byte address op codes by their associated 4byte address versions. Using the dedicated 4byte address op codes doesn't change the internal state of the SPI NOR memory as opposed to using other means such as updating a Base Address Register (BAR) and sending command to enter/leave the 4byte mode. Hence when a CPU reset occurs, early bootloaders don't need to be aware of BAR value or 4byte mode being enabled: they can still access the first 16MiB of the SPI NOR memory using the regular 3byte address op codes. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Tested-by: Vignesh R <vigneshr@ti.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2017-09-25mtd: spi-nor: rename SPINOR_OP_* macros of the 4-byte address op codesAlison Wang
This patch renames the SPINOR_OP_* macros of the 4-byte address instruction set so the new names all share a common pattern: the 4-byte address name is built from the 3-byte address name appending the "_4B" suffix. The patch also introduces new op codes to support other SPI protocols such as SPI 1-4-4 and SPI 1-2-2. This is a transitional patch and will help a later patch of spi-nor.c to automate the translation from the 3-byte address op codes into their 4-byte address version. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2017-09-25mtd: spi-nor: remove WARN_ONCE() message in spi_nor_write()Cyrille Pitchen
This patch removes the WARN_ONCE() test in spi_nor_write(). This macro triggers the display of a warning message almost every time we use a UBI file-system because a write operation is performed at offset 64, which is in the middle of the SPI NOR memory page. This is a valid operation for ubifs. Hence this warning is pretty annoying and useless so we just remove it. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Suggested-by: Richard Weinberger <richard@nod.at> Suggested-by: Andras Szemzo <szemzo.andras@gmail.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
2017-09-25mtd: spi-nor: improve macronix_quad_enable()Cyrille Pitchen
The patch checks whether the Quad Enable bit is already set in the Status Register. If so, the function exits immediately with a successful return code. Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Marek Vasut <marek.vasut@gmail.com>
2017-09-25spi-nor: Add support for S3AN spi-nor devicesAlison Wang
Xilinx Spartan-3AN FPGAs contain an In-System Flash where they keep their configuration data and (optionally) some user data. The protocol of this flash follows most of the spi-nor standard. With the following differences: - Page size might not be a power of two. - The address calculation (default addressing mode). - The spi nor commands used. Protocol is described on Xilinx User Guide UG333 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: Fix typo: "occured" -> "occurred"Nobuhiro Iwamatsu
Trivial typo fix in comment. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
2017-09-25mtd: spi-nor: Add support for mr25h40IWAMOTO Masahiko
Add Everspin mr25h40 512KB MRAM to the list of supported chips. Signed-off-by: Masahiko Iwamoto <iwamoto@allied-telesis.co.jp> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Add support for N25Q016AMoritz Fischer
This commit adds support in the spi-nor driver for the N25Q016A, a 16Mbit SPI NOR flash from Micron. Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Jagan Teki <jteki@openedev.com> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: Add at25df321 spi-nor flash supportJagan Teki
Add Atmel at25df321 spi-nor flash to the list of spi_nor_ids. Cc: Brian Norris <computersforpeace@gmail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: add support for s25fl208kSean Nyekjaer
Signed-off-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: fix flags for s25fl128sAlison Wang
The Spansion S25FL128S also supports dual read mode. In addition remove flag SECT_4K. 4K erases are supported, but not uniformly. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: add Macronix mx25u25635f to list of known devices.Ash Benz
Signed-off-by: Ash Benz <ash.benz@bk.ru> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: fsl-quad: allow sub node probe failedYuan Yao
The QSPI can support max to four spi flash at the same time. But sometime one or more flash maybe probe failed because of the wrong setting or the hardware issue or some othere. But as long as there is one flash probe success, that the QSPI driver should probe success and finish all the initialization. Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
2017-09-25spi-nor: fslquad: add quad mode read for s25fs512sAlison Wang
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
2017-09-25mtd: spi-nor: fsl-quad: Add flash S25FS extra supportYunhui Cui
There are some boards have the same QSPI controller but have different vendor falsh, So as to controller can use the same compatible and share the driver, Just for different flash to do the appropriate adaptation. Based on this, we need add the vendor field in spi-nor, Because we will use the field to distribute corresponding LUT for different flash operations. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
2017-09-25driver: spi: fsl-quad: Hang memcpy: Unhandled fault: alignment faultAlison Wang
vmap/iomap based on whether the buffer is in memory region or reserved region.However, both map it as non-cacheable memory.For armv8 specifically, non-cacheable mapping requests use a memory type that has to be accessed aligned to the request size.memcpy() doesn't guarantee that. memcpy_toio() can guarantee 4-bytes alignment. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd: fsl-quadspi: add DDR quad read for SpansionYunhui Cui
Add the DDR quad read support for the fsl-quadspi driver. And, add the Spansion s25fl128s NOR flash ddr quad mode support. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd: fsl-quadspi: Add quad mode for flash n25q128Yunhui Cui
Add some lut_tables to support quad mode for flash n25q128 on the board ls1021a-twr and solve flash Spansion and Micron command conflict. In switch {}, The value of command SPINOR_OP_RD_EVCR and SPINOR_OP_SPANSION_RDAR is the same. They have to share the same seq_id: SEQID_RDAR_OR_RD_EVCR. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd: fsl-quadspi: add multi flash chip R/W on ls2080aYunhui Cui
There is a hardware feature that qspi_amba_base is added internally by SOC design on ls2080a. so memmap_phy need not be added in driver. If memmap_phy is added, the flash A1 addr space is [0, memmap_phy] which far more than flash size. The AMBA memory will be divided into four parts and assign to every chipselect. Every channel will has two valid chipselects. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd: fsl-quadspi: disable AHB buffer prefetchYunhui Cui
A-009282: QuadSPI: QuadSPI data pre-fetch can result in incorrect data Affects: QuadSPI Description: With AHB buffer prefetch enabled, the QuadSPI may return incorrect data on the AHB interface. The buffer pre-fetch is enabled if the fetch size as configured either in the LUT or in the BUFxCR register is greater than 8 bytes. Impact: Only 64 bit read allowed. Workaround: Keep the read data size to 64 bits (8 Bytes), which disables the prefetch on the AHB buffer, and prevents this issue from occurring. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd: spi-nor: fsl-quadspi: extend support for some special requerment.Yunhui Cui
Add extra info in LUT table to support some special requerments. Spansion S25FS-S family flash need some special operations. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd: spi-nor: fsl-quadspi:Support qspi for ls2080aYunhui Cui
There is a hardware feature that qspi_amba_base is added internally by SOC design on ls2080a. So as to software, the driver need support to the feature. Signed-off-by: Yunhui Cui <B56489@freescale.com> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-09-25mtd:spi-nor:fsl-quadspi:Add fast-read mode supportYunhui Cui
The qspi driver add generic fast-read mode for different flash venders. There are some different board flash work on different mode, such fast-read, quad-mode. So we have to modify the third entrace parameter of spi_nor_scan(). Signed-off-by: Yunhui Cui <B56489@freescale.com>
2017-09-25mtd: fsl-quadspi: Rename SEQID_QUAD_READ to SEQID_READYunhui Cui
There are some read modes for flash, such as NORMAL, FAST, QUAD, DDR QUAD. These modes will use the identical lut table base So rename SEQID_QUAD_READ to SEQID_READ. Signed-off-by: Yunhui Cui <B56489@freescale.com> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd:fsl-quadspi:use the property fields of SPI-NORYunhui Cui
We can get the read/write/erase opcode from the spi nor framework directly. This patch uses the information stored in the SPI-NOR to remove the hardcode in the fsl_qspi_init_lut(). Signed-off-by: Yunhui Cui <B56489@freescale.com> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Acked-by: Han xu <han.xu@nxp.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25mtd: spi-nor: constify fsl_qspi_devtype_dataLABBE Corentin
All fsl_qspi_devtype_data structures are never modified. This patch constify them. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Acked-by: Han Xu <han.xu@nxp.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
2017-09-25spi: spi-fsl-dspi: Fix continuous selection formatSanchayan Maity
Current DMA implementation was not handling the continuous selection format viz. SPI chip select would be deasserted even between sequential serial transfers. Use existing dspi_data_to_pushr function to restructure the transmit code path and set or reset the CONT bit on same lines as code path in EOQ mode does. This correctly implements continuous selection format while also correcting and cleaning up the transmit code path. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-09-25spi: spi-fsl-dspi: Fix incorrect DMA setupSanchayan Maity
Currently dmaengine_prep_slave_single was being called with length set to the complete DMA buffer size. This resulted in unwanted bytes being transferred to the SPI register leading to clock and MOSI lines having unwanted data even after chip select got deasserted and the required bytes having been transferred. While at it also clean up the use of curr_xfer_len which is central to the DMA setup, from bytes to DMA transfers for every use. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Reviewed-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Mark Brown <broonie@kernel.org>
2017-09-25spi: spi-fsl-dspi: Fix error handlingChristophe JAILLET
According to error handling in this function, it is likely that going to 'out_master_put' was expected here. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
2017-09-25spi: SPI_FSL_DSPI should depend on HAS_DMAGeert Uytterhoeven
If NO_DMA=y: ERROR: "bad_dma_ops" [drivers/spi/spi-fsl-dspi.ko] undefined! Add a dependency on HAS_DMA to fix this. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Zhikang Zhang <zhikang.zhang@nxp.com>
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