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AgeCommit message (Expand)Author
2014-09-30Merge branch 'topic/skl-stage1' into drm-intel-next-queuedDaniel Vetter
2014-09-30drm/i915: preserve other DP_TEST_SINK bits.Rodrigo Vivi
2014-09-30drm/i915/bdw: WaDisableFenceDestinationToSLMRodrigo Vivi
2014-09-30drm/i915: Add IS_BDW_GT3 macro.Rodrigo Vivi
2014-09-30drm/i915: Fix Sink CRCRodrigo Vivi
2014-09-29drm/i915: Broadwell DDI Buffer translation - more tuningRodrigo Vivi
2014-09-29drm/i915: Broadwell DDI Buffer translation changed to give better margin.Rodrigo Vivi
2014-09-29drm/i915: Make sure PSR is ready for been re-enabled.Rodrigo Vivi
2014-09-29drm/i915: Minimize the huge amount of unecessary fbc sw cache clean.Rodrigo Vivi
2014-09-24drm/i915: Avoid re-configure panel on every PSR re-enable.Rodrigo Vivi
2014-09-24drm/i915/skl: Move gen9 pm initialization into its own branchDamien Lespiau
2014-09-24drm/i915/skl: Introduce intel_num_planes()Damien Lespiau
2014-09-24drm/i915/skl: Introduce a I915_MAX_PLANES macroDamien Lespiau
2014-09-24drm/i915/skl: Adjust assert_sprites_disabled()Damien Lespiau
2014-09-24drm/i915/skl: Implement drm_plane vfuncsDamien Lespiau
2014-09-24drm/i915/skl: Skylake has 2 "sprite" planes per pipeDamien Lespiau
2014-09-24drm/i915/skl: Implement WaDisableDgMirrorFixInHalfSliceChicken5:sklDamien Lespiau
2014-09-24drm/i915/skl: Implement Wa4x4STCOptimizationDisable:sklDamien Lespiau
2014-09-24drm/i915/skl: Implement WaDisableSDEUnitClockGating:sklDamien Lespiau
2014-09-24drm/i915/skl: Sunrise Point PCH detectionSatheeshakrishna M
2014-09-24drm/i915/skl: Adjust the display engine interruptsDamien Lespiau
2014-09-24drm/i915/skl: Restore pipe B/C interruptsSatheeshakrishna M
2014-09-24drm/i915/skl: SKL backlight enablingSatheeshakrishna M
2014-09-24drm/i915/skl: vfuncs for skl eld and global resourceSatheeshakrishna M
2014-09-24drm/i915/skl: SKL pipe misc programmingSatheeshakrishna M
2014-09-24drm/i915/skl: SKL shares the same underrun interrupt as BDWDamien Lespiau
2014-09-24drm/i915/skl: Report the PDP regs as in gen8Damien Lespiau
2014-09-24drm/i915/skl: report the same INSTDONE registers as gen8Damien Lespiau
2014-09-24drm/i915/skl: Allow the reg_read ioctl to return RCS_TIMESTAMPDamien Lespiau
2014-09-24drm/i915/skl: Initialize PPGTT like gen8Damien Lespiau
2014-09-24drm/i915/skl: Provide a get_aux_send_ctl() vfunc for skylakeDamien Lespiau
2014-09-24drm/i915/skl: Implement the get_aux_clock_divider() DP vfuncDamien Lespiau
2014-09-24drm/i915/skl: gen9 uses the same bind_vma() vfuncs as gen6+Damien Lespiau
2014-09-24drm/i915/skl: Add the additional graphics stolen sizesDamien Lespiau
2014-09-24drm/i915/skl: Skylake moves AUX_CTL from PCH to CPUDamien Lespiau
2014-09-24drm/i915/skl: Add support for DP voltage swings and pre-emphasisDamien Lespiau
2014-09-24drm/i915/skl: Program the DDI buffer translation tablesDamien Lespiau
2014-09-24drm/i915/skl: Don't try to read out the PCH transcoder state if not presentDamien Lespiau
2014-09-24drm/i915/skl: Don't create a VGA connector on SkylakeDamien Lespiau
2014-09-24drm/i915/skl: Implement the new update_plane() for primary planesDamien Lespiau
2014-09-24drm/i915/skl: i915_swizzle_info gen9 fixRobert Beckett
2014-09-24drm/i915/skl: Framebuffers need to be aligned to 256KB on SkylakeDamien Lespiau
2014-09-24drm/i915/skl: don't set the AsyncFlip performance mode for Gen9+Imre Deak
2014-09-24drm/i915/skl: Skylake shares the interrupt logic with BroadwellDamien Lespiau
2014-09-24drm/i915/skl: Provide a placeholder for init_clock_gating()Damien Lespiau
2014-09-24drm/i915/skl: Fence registers on SKL are the same as SNBDamien Lespiau
2014-09-24drm/i915/skl: SKL FBC enablementDaisy Sun
2014-09-24drm/i915/skl: Add an IS_SKYLAKE macroSatheeshakrishna M
2014-09-24drm/i915/skl: Add an IS_GEN9() defineDamien Lespiau
2014-09-24drm/i915/skl: Add the Skylake PCI idsDamien Lespiau
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