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2015-11-23ARC: dw2 unwind: Remove falllback linear search thru FDE entriesVineet Gupta
Fixes STAR 9000953410: "perf callgraph profiling causing RCU stalls" | perf record -g -c 15000 -e cycles /sbin/hackbench | | INFO: rcu_preempt self-detected stall on CPU | 1: (1 GPs behind) idle=609/140000000000002/0 softirq=2914/2915 fqs=603 | Task dump for CPU 1: in-kernel dwarf unwinder has a fast binary lookup and a fallback linear search (which iterates thru each of ~11K entries) thus takes 2 orders of magnitude longer (~3 million cycles vs. 2000). Routines written in hand assembler lack dwarf info (as we don't support assembler CFI pseudo-ops yet) fail the unwinder binary lookup, hit linear search, failing nevertheless in the end. However the linear search is pointless as binary lookup tables are created from it in first place. It is impossible to have binary lookup fail while succeed the linear search. It is pure waste of cycles thus removed by this patch. This manifested as RCU stalls / NMI watchdog splat when running hackbench under perf with callgraph profiling. The triggering condition was perf counter overflowing in routine lacking dwarf info (like memset) leading to patheic 3 million cycle unwinder slow path and by the time it returned new interrupts were already pending (Timer, IPI) and taken rightaway. The original memset didn't make forward progress, system kept accruing more interrupts and more unwinder delayes in a vicious feedback loop, ultimately triggering the NMI diagnostic. Cc: stable@vger.kernel.org Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-11-17ARC: remove SYNC from __switch_to()Vineet Gupta
SYNC in __switch_to() is a historic relic and not needed at all. - In UP context it is obviously useless, why would we want to stall the core for all updates to stack memory of t0 to complete before loading kernel mode callee registers from t1 stack's memory. - In SMP, there could be potential race in which outgoing task could be concurrently picked for running on a different core, thus writes to stack here need to be visible before the reads from stack on other core. Peter confirmed that generic schedular already has needed barriers (by way of rq lock) so there is no need for additional arch barrier. This came up when Noam was trying to replace this SYNC with EZChip specific hardware thread scheduling instruction for their platform support. Link: http://lkml.kernel.org/r/20151102092654.GM17308@twins.programming.kicks-ass.net Cc: Peter Zijlstra <peterz@infradead.org> Cc: linux-kernel@vger.kernel.org Cc: Noam Camus <noamc@ezchip.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-11-16ARCv2: Use the default irq priority for idle sleepVineet Gupta
Although kernel doesn't support the multiple IRQ priority levels provided by HS38x core intc yet, ensure that the default prio value is used anyways by relevant code. SLEEP insn needs to be provided the IRQ priority level which can interrupt it. This needs to be the default level which maynot necessarily be 0 as assumed by current code. This change allows a kernel with ARCV2_IRQ_DEF_PRIO = 1 to boot fine. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-11-16ARC: Abstract out ISA specific SLEEP argsVineet Gupta
No semantical changes, prepares for ARCv2 specific change in next commit Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-11-16ARC: comments updateVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-11-16ARC: switch to arc-linux- CROSS_COMPILE prefix across all configssujayraaj
When building kernel with buildroot built toolchain, CROSS_COMPILE currently needs adjustment even if minor. This is because the defconfigs prefer "arc-linux-uclibc-" prefix from hand built (non buildroot) toolchain while buildroot provides "arc-buildroot-linux-uclibc-" To avoid this use the common "arc-linux-" prefix which is provided by buildroot and has also been in hand built tools for quite some time. Signed-off-by: sujayraaj <sujayraaj@gmail.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com> [vgupta: updated changelog]
2015-11-14Merge tag 'arc-4.4-rc1-part2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC fixes from Vineet Gupta: "Found a couple of brown paper bag bugs with the prev pull request (including a SMP build breakage report from Guenter). Since these are urgent I also decided to send over a bunch of other pending fixes which could have otherwise waited an rc or two. Summary: - A bunch of brown paper bag bugs (MAINTAINERS list email, SMP build failure) - cpu_relax() now compiler barrier for UP as well - handling of userspace Bus Errors for ARCompact builds" * tag 'arc-4.4-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: ARC: Fix silly typo in MAINTAINERS file ARC: cpu_relax() to be compiler barrier even for UP ARC: use ASL assembler mnemonic ARC: [arcompact] Handle bus error from userspace as Interrupt not exception ARC: remove extraneous header include ARCv2: lib: memcpy: use local symbols
2015-11-14ARC: cpu_relax() to be compiler barrier even for UPVineet Gupta
cpu_relax() on ARC has been barrier only for SMP (and no-op for UP). Per recent discussions, it is safer to make it a compiler barrier unconditionally. Link: http://lkml.kernel.org/r/53A7D3AA.9020100@synopsys.com Acked-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-11-14ARC: use ASL assembler mnemonicVineet Gupta
ARCompact and ARCv2 only have ASL, while binutils used to support LSL as a alias mnemonic. Newer binutils (upstream) don't want to do that so replace it. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-11-14ARC: [arcompact] Handle bus error from userspace as Interrupt not exceptionVineet Gupta
Bus errors from userspace on ARCompact based cores are handled by core as a high priority L2 interrupt but current code treated it as interrupt Handling an interrupt like exception is certainly not going to go unnoticed. (and it worked so far as we never saw a Bus error from userspace until IPPK guys tested a DDR controller with ECC error detection etc hence needed to explicitly trigger/handle such errors) - So move mem_service exception handler from common code into ARCv2 code. - In ARCompact code, define mem_service as L2 interrupt handler which just drops down to pure kernel mode and goes of to enqueue SIGBUS Reported-by: Nelson Pereira <npereira@synopsys.com> Tested-by: Ana Martins <amartins@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-11-14ARC: remove extraneous header includeVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-11-06Merge tag 'devicetree-for-4.4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull DeviceTree updates from Rob Herring: "A fairly large (by DT standards) pull request this time with the majority being some overdue moving DT binding docs around to consolidate similar bindings. - DT binding doc consolidation moving similar bindings to common locations. The majority of these are display related which were scattered in video/, fb/, drm/, gpu/, and panel/ directories. - Add new config option, CONFIG_OF_ALL_DTBS, to enable building all dtbs in the tree for most arches with dts files (except powerpc for now). - OF_IRQ=n fixes for user enabled CONFIG_OF. - of_node_put ref counting fixes from Julia Lawall. - Common DT binding for wakeup-source and deprecation of all similar bindings. - DT binding for PXA LCD controller. - Allow ignoring failed PCI resource translations in order to ignore 64-bit addresses on non-LPAE 32-bit kernels. - Support setting the NUMA node from DT instead of only from parent device. - Couple of earlycon DT parsing fixes for address and options" * tag 'devicetree-for-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (45 commits) MAINTAINERS: update DT binding doc locations devicetree: add Sigma Designs vendor prefix of: simplify arch_find_n_match_cpu_physical_id() function Documentation: arm: Fixed typo in socfpga fpga mgr example Documentation: devicetree: fix reference to legacy wakeup properties Documentation: devicetree: standardize/consolidate on "wakeup-source" property drivers: of: removing assignment of 0 to static variable xtensa: enable building of all dtbs mips: enable building of all dtbs metag: enable building of all dtbs metag: use common make variables for dtb builds h8300: enable building of all dtbs arm64: enable building of all dtbs arm: enable building of all dtbs arc: enable building of all dtbs arc: use common make variables for dtb builds of: add config option to enable building of all dtbs of/fdt: fix error checking for earlycon address of/overlay: add missing of_node_put of/platform: add missing of_node_put ...
2015-11-04Merge branch 'locking-core-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull locking changes from Ingo Molnar: "The main changes in this cycle were: - More gradual enhancements to atomic ops: new atomic*_read_ctrl() ops, synchronize atomic_{read,set}() ordering requirements between architectures, add atomic_long_t bitops. (Peter Zijlstra) - Add _{relaxed|acquire|release}() variants for inc/dec atomics and use them in various locking primitives: mutex, rtmutex, mcs, rwsem. This enables weakly ordered architectures (such as arm64) to make use of more locking related optimizations. (Davidlohr Bueso) - Implement atomic[64]_{inc,dec}_relaxed() on ARM. (Will Deacon) - Futex kernel data cache footprint micro-optimization. (Rasmus Villemoes) - pvqspinlock runtime overhead micro-optimization. (Waiman Long) - misc smaller fixlets" * 'locking-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: ARM, locking/atomics: Implement _relaxed variants of atomic[64]_{inc,dec} locking/rwsem: Use acquire/release semantics locking/mcs: Use acquire/release semantics locking/rtmutex: Use acquire/release semantics locking/mutex: Use acquire/release semantics locking/asm-generic: Add _{relaxed|acquire|release}() variants for inc/dec atomics atomic: Implement atomic_read_ctrl() atomic, arch: Audit atomic_{read,set}() atomic: Add atomic_long_t bitops futex: Force hot variables into a single cache line locking/pvqspinlock: Kick the PV CPU unconditionally when _Q_SLOW_VAL locking/osq: Relax atomic semantics locking/qrwlock: Rename ->lock to ->wait_lock locking/Documentation/lockstat: Fix typo - lokcing -> locking locking/atomics, cmpxchg: Privatize the inclusion of asm/cmpxchg.h
2015-11-03Merge tag 'arc-4.4-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc Pull ARC updates from Vineet Gupta: - Support for new MM features in ARCv2 cores (THP, PAE40) Some generic THP bits are touched - all ACKed by Kirill - Platform framework updates to prepare for EZChip arrival (still in works) - ARC Public Mailing list setup finally (linux-snps-arc@lists.infraded.org) * tag 'arc-4.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc: (42 commits) ARC: mm: PAE40 support ARC: mm: PAE40: tlbex.S: Explicitify the size of pte_t ARC: mm: PAE40: switch to using phys_addr_t for physical addresses ARC: mm: HIGHMEM: populate high memory from DT ARC: mm: HIGHMEM: kmap API implementation ARC: mm: preps ahead of HIGHMEM support #2 ARC: mm: preps ahead of HIGHMEM support ARC: mm: use generic macros _BITUL()/_AC() ARC: mm: Improve Duplicate PD Fault handler MAINTAINERS: Add public mailing list for ARC ARC: Ensure DT mem base is same as what kernel is built with ARC: boot: Non Master cpus only need to call EARLY_CPU_SETUP once ARCv2: smp: [plat-*]: No need to explicitly call mcip_init_smp() ARC: smp: Introduce smp hook @init_irq_cpu called for all cores ARC: smp: Rename platform hook @init_smp -> @init_cpu_smp ARCv2: smp: [plat-*]: No need to explicitly call mcip_init_early_smp() ARC: smp: Introduce smp hook @init_early_smp for Master core ARC: remove @init_time, @init_irq platform callbacks ARC: smp: irqchip: handle IPI as percpu irq like timer ARC: boot: Support Halt-on-reset and Run-on-reset SMP booting modes ...
2015-11-03ARCv2: lib: memcpy: use local symbolsVineet Gupta
Otherwise perf profiles don't charge tme to memcpy Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-29ARC: mm: PAE40 supportVineet Gupta
This is the first working implementation of 40-bit physical address extension on ARCv2. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: mm: PAE40: tlbex.S: Explicitify the size of pte_tVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: mm: PAE40: switch to using phys_addr_t for physical addressesVineet Gupta
That way a single flip of phys_addr_t to 64 bit ensures all places dealing with physical addresses get correct data Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: mm: HIGHMEM: populate high memory from DTVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: mm: HIGHMEM: kmap API implementationVineet Gupta
Implement kmap* API for ARC. This enables - permanent kernel maps (pkmaps): :kmap() API - fixmap : kmap_atomic() We use a very simple/uniform approach for both (unlike some of the other arches). So fixmap doesn't use the customary compile time address stuff. The important semantic is sleep'ability (pkmap) vs. not (fixmap) which the API guarantees. Note that this patch only enables highmem for subsequent PAE40 support as there is no real highmem for ARC in pure 32-bit paradigm as explained below. ARC has 2:2 address split of the 32-bit address space with lower half being translated (virtual) while upper half unstranslated (0x8000_0000 to 0xFFFF_FFFF). kernel itself is linked at base of unstranslated space (i.e. 0x8000_0000 onwards), which is mapped to say DDR 0x0 by external Bus Glue logic (outside the core). So kernel can potentially access 1.75G worth of memory directly w/o need for highmem. (the top 256M is taken by uncached peripheral space from 0xF000_0000 to 0xFFFF_FFFF) In PAE40, hardware can address memory beyond 4G (0x1_0000_0000) while the logical/virtual addresses remain 32-bits. Thus highmem is required for kernel proper to be able to access these pages for it's own purposes (user space is agnostic to this anyways). Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: mm: preps ahead of HIGHMEM support #2Vineet Gupta
Explicit'ify that all memory added so far is low memory Nothing semantical Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: mm: preps ahead of HIGHMEM supportVineet Gupta
Before we plug in highmem support, some of code needs to be ready for it - copy_user_highpage() needs to be using the kmap_atomic API - mk_pte() can't assume page_address() - do_page_fault() can't assume VMALLOC_END is end of kernel vaddr space Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: mm: use generic macros _BITUL()/_AC()Alexey Brodkin
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: mm: Improve Duplicate PD Fault handlerVineet Gupta
- Move the verbosity knob from .data to .bss by using inverted logic - No need to readout PD1 descriptor - clip the non pfn bits of PD0 to avoid clipping inside the loop Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: Ensure DT mem base is same as what kernel is built withVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: boot: Non Master cpus only need to call EARLY_CPU_SETUP onceVineet Gupta
With prev fixes, all cores now start via common entry point @stext which already calls EARLY_CPU_SETUP for all cores - so no need to invoke it again Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARCv2: smp: [plat-*]: No need to explicitly call mcip_init_smp()Vineet Gupta
MCIP now registers it's own per cpu setup routine (for IPI IRQ request) using smp_ops.init_irq_cpu(). So no need for platforms to do that. This now completely decouples platforms from MCIP. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: smp: Introduce smp hook @init_irq_cpu called for all coresVineet Gupta
Note this is not part of platform owned static machine_desc, but more of device owned plat_smp_ops (rather misnamed) which a IPI provider or some such typically defines. This will help us seperate out the IPI registration from platform specific init_cpu_smp() into device specific init_irq_cpu() Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: smp: Rename platform hook @init_smp -> @init_cpu_smpVineet Gupta
This conveys better that it is called for each cpu Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARCv2: smp: [plat-*]: No need to explicitly call mcip_init_early_smp()Vineet Gupta
MCIP now registers it's own probe callback with smp_ops.init_early_smp() which is called by ARC common code, so no need for platforms to do that. This decouples the platforms and MCIP and helps confine MCIP details to it's own file. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: smp: Introduce smp hook @init_early_smp for Master coreVineet Gupta
This adds a platform agnostic early SMP init hook which is called on Master core before calling setup_processor() setup_arch() smp_init_cpus() smp_ops.init_early_smp() ... setup_processor() How this helps: - Used for one time init of certain SMP centric IP blocks, before calling setup_processor() which probes various bits of core, possibly including this block - Currently platforms need to call this IP block init from their init routines, which doesn't make sense as this is specific to ARC core and not platform and otherwise requires copy/paste in all (and hence a possible point of failure) e.g. MCIP init is called from 2 platforms currently (axs10x and sim) which will go away once we have this. This change only adds the hooks but they are empty for now. Next commit will populate them and remove the explicit init calls from platforms. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: remove @init_time, @init_irq platform callbacksVineet Gupta
These are not in use for ARC platforms. Moreover DT mechanims exist to probe them w/o explicit platform calls. - clocksource drivers can use CLOCKSOURCE_OF_DECLARE() - intc IRQCHIP_DECLARE() calls + cascading inside DT allows external intc to be probed automatically Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: smp: irqchip: handle IPI as percpu irq like timerVineet Gupta
The reason this was not done so far was lack of genuine IPI_IRQ for ARC700, as we don't have a SMP version of core yet (which might change soon thx to EZChip). Nevertheles to increase the build coverage, we need to allow CONFIG_SMP for ARC700 and still be able to run it on a UP platform (nsim or AXS101) with a UP Device Tree (SMP-on-UP) The build itself requires some define for IPI_IRQ and even a dummy value is fine since that code won't run anyways. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-28ARC: boot: Support Halt-on-reset and Run-on-reset SMP booting modesVineet Gupta
For Run-on-reset, non masters need to spin wait. For Halt-on-reset they can jump to entry point directly. Also while at it, made reset vector handler as "the" entry point for kernel including host debugger based boot (which uses the ELF header entry point) Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-27arc: enable building of all dtbsRob Herring
Enable building all dtb files when CONFIG_OF_ALL_DTBS is enabled. The dtbs are not really dependent on a platform being enabled or any other kernel config, so for testing coverage it is convenient to build all of the dtbs. This builds all dts files in the tree, not just targets listed. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-27arc: use common make variables for dtb buildsRob Herring
Use dtb-y and always make variables to build dtbs instead of explicit dtbs rule. This is in preparation to support building all dtbs. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-26arc: axs10x_defconfig: remove CONFIG_MMC_DW_IDMACShawn Lin
DesignWare MMC Controller's transfer mode should be decided at runtime instead of compile-time. So we remove this config option and read dw_mmc's register to select DMA master. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Acked-by: Vineet Gupta <vgupta@synopsys.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2015-10-17ARC: smp: Move default boot kick/wait code out of MCIP into common codeVineet Gupta
For non halt-on-reset case, all cores start of simultaneously in @stext. Master core0 proceeds with kernel boot, while other spin-wait on @wake_flag being set by master once it is ready. So NO hardware assist is needed for master to "kick" the others. This patch moves this soft implementation out of mcip.c (as there is no hardware assist) into common smp.c Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARC: boot log: decode more mmu config itemsVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARC: boot log: move helper macros to header for reuseVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARC: mm: compute TLB size as needed from ways * setsVineet Gupta
This frees up some bits to hold more high level info such as PAE being present, w/o increasing the size of already bloated cpuinfo struct Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARC: mm: MMU v1..v3 only selectable for ARCompact ISA based coresVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARC: make write_aux_reg safer against macro substitutionVineet Gupta
It was generating warnings when called as write_aux_reg(x, paddr >> 32) Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARC: [arcompact] entry.S: Elide extra check/branch in exception ret pathVineet Gupta
This is done by improving the laddering logic ! Before: if Exception goto excep_or_pure_k_ret if !Interrupt(L2) goto l1_chk else INTERRUPT_EPILOGUE 2 l1_chk: if !Interrupt(L1) (i.e. pure kernel mode) goto excep_or_pure_k_ret else INTERRUPT_EPILOGUE 1 excep_or_pure_k_ret: EXCEPTION_EPILOGUE Now: if !Interrupt(L1 or L2) (i.e. exception or pure kernel mode) goto excep_or_pure_k_ret ; guaranteed to be an interrupt if !Interrupt(L2) goto l1_ret else INTERRUPT_EPILOGUE 2 ; by virtue of above, no need to chk for L1 active l1_ret: INTERRUPT_EPILOGUE 1 excep_or_pure_k_ret: EXCEPTION_EPILOGUE Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARC: [arcompact] entry.S: Document preemption games for L2 intrVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARC: [arcompact] entry.S: Improve early return from exceptionVineet Gupta
The requirement is to - Reenable Exceptions (AE cleared) - Reenable Interrupts (E1/E2 set) We need to do wiggle these bits into ERSTATUS and call RTIE. Prev version used the pre-exception STATUS32 as starting point for what goes into ERSTATUS. This required explicit fixups of U/DE/L bits. Instead, use the current (in-exception) STATUS32 as starting point. Being in exception handler U/DE/L can be safely assumed to be correct. Only AE/E1/E2 need to be fixed. So the new implementation is slightly better -Avoids read form memory -Is 4 bytes smaller for the typical 1 level of intr configuration -Depicts the semantics more clearly Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARC: [arcompact] don't check for hard isr calling local_irq_enable()Vineet Gupta
Historically this was done by ARC IDE driver, which is long gone. IRQ core is pretty robust now and already checks if IRQs are enabled in hard ISRs. Thus no point in checking this in arch code, for every call of irq enabled. Further if some driver does do that - let it bring down the system so we notice/fix this sooner than covering up for sucker This makes local_irq_enable() - for L1 only case atleast simple enough so we can inline it. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARCv2: mm: THP: flush_pmd_tlb_range make SMP safeVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARCv2: mm: THP: Implement flush_pmd_tlb_range() optimizationVineet Gupta
Implement the TLB flush routine to evict a sepcific Super TLB entry, vs. moving to a new ASID on every such flush. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
2015-10-17ARCv2: mm: THP: boot validation/reportingVineet Gupta
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>