| Age | Commit message (Collapse) | Author |
|---|
|
Add esdhc node for ls1088a and enable it on both RDB and QDS boards.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
|
|
Currently SD UHS-I modes were enabled by default on LS208xARDB boards,
but the new LS2088ARDB RevF board didn't support them any more since SDHC
circuit had been reworked. This patch is to disable SD UHS-I modes by default
in case of any issue on LS2088ARDB RevF
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
Acked-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
1. Remove ls1043a compatible string from node
2. Fix the sata ecc register address error
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
|
|
LS208xA has a SEC v5.1 security engine.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
|
|
aliases node is identical for all boards, thus move it
to the common file ls208xa.dtsi.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
|
|
LS1088A has a SEC v5.3 security engine.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
|
|
Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
|
|
Add mdio and phy nodes for the following FSL platforms:
- LS1088A RDB
- LS2080A QDS & RDB
- LS2088A QDS, RDB & simu
Contains contributions from patches by the following authors:
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
|
|
Signed-off-by: Constantin Tudor <constantin.tudor@nxp.com>
|
|
Add "configure-gfladj" boolean property to USB3 node. This property
is used to determine whether frame length adjustent is required
or not
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
|
|
Some DWC3 platform has DMA snooping feature.
Therefore, add property "snps,dma-snooping" to enable it.
Signed-off-by: Changming Huang <jerry.huang@nxp.com>
|
|
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
|
|
There are eight cores in ls1088a and each core has an watchdog,
ls1088a can use sp805-wdt driver, so we just add DT node for it.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
|
|
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
|
|
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
|
|
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
|
|
Add rcpm and ftm0 nodes. The Power Management related features
need these nodes.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
|
|
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
|
|
PCA954x Mux device should never be turned-off after power-on. if
device tree contians "i2c-mux-never-disable" property for pca954x
device node, it can ensure that skip disabling PCA954x Mux device.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
|
|
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
`
|
|
update sata node to add the ecc register address and dma-coherent
properties.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
|
|
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
|
|
ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
|
|
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
|
|
This is temporary patch, will rewrite for open source
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
|
|
There is a s25fs512s qspi flash on QDS, RDB and FRDM board.
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
|
|
LS1088a implements 3 PCIe 3.0 controllers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
|
|
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
|
|
The physical memory map address and CCSR registers map address are
different between LS2088A and other LS2080A series SoCs.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
|
LS1046a implements 3 PCIe 3.0 controllers.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
|
Some platforms(NXP Layerscape for example) aer/pme interrupts was not
MSI/MSI-X/INTx but using interrupt line independently. This patch
add "aer", "pme" interrupt-names for aer/pme interrupt.
With the interrupt-names "aer", "pme" code could probe aer/pme interrupt
line for pcie root port, replace the aer/pme interrupt service irqs.
This is intend to fixup the Layerscape platforms which aer/pmes interrupts
was not MSI/MSI-X/INTx, but using interrupt line independently.
Since the interrupt-names "intr" never been used. Remove it.
Signed-off-by: Po Liu <po.liu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
|
add ds26522 node to fsl-ls1043a-rdb.dts
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
|
|
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
|
|
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
|
|
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
|
|
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
|
|
fsl-mc bus support the new iommu-map property. Comply to this binding
for fsl_mc bus.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
|
|
LS1046a includes 3 MSI controllers.
Each controller supports 128 interrupts.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
|
In order to maximize the use of MSI, a PCIe controller will share
all MSI controllers. The patch changes "msi-parent" to refer to all
MSI controller dts nodes.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
|
"1" should be replaced by "l". This is a typo.
The patch is to fix it.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
|
|
There are two eSDHC controllers in LS1012A. This patch is to add
eSDHC nodes for ls1012a dts. Also enable eSDHC for RDB/QDS boards.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
|
This patch is to enable SD UHS-I mode on LS208xRDB and eMMC HS200
mode on LS208xQDS in dts. Also, the eSDHC peripheral clock must be
used instead of platform clock to support these modes.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
|
This patch is to enable SD UHS-I mode and eMMC HS200 mode on
LS1046ARDB in dts. Also, the eSDHC peripheral clock must be used
instead of platform clock to support these modes.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
|
|
Update the copyright claims to comply with company policy.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
|
|
LS1088A contains eight ARM v8 CortexA53 processor cores
with 32 KB L1-D cache and 32 KB L1-I cache
Features summary
Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
- Arranged as two clusters of four cores sharing a 1 MB L2 cache
- Speed Up to 1.5 GHz
- Support for cluster power-gating.
Cache coherent interconnect (CCI-400)
- Hardware-managed data coherency
- Up to 700 MHz
One 64-bit DDR4 SDRAM memory controller with ECC
Data path acceleration architecture 2.0 (DPAA2)
Three PCIe 3.0 controllers
One serial ATA (SATA 3.0) controller
Three high-speed USB 3.0 controllers with integrated PHY
Following levels of DTSI/DTS files have been created for the LS1088A
SoC family:
- fsl-ls1088a.dtsi:
DTS-Include file for NXP LS1088A SoC.
- fsl-ls1088a-qds.dts:
DTS file for NXP LS1088A QDS board.
- fsl-ls1088a-rdb.dts:
DTS file for NXP LS1088A RDB board
Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>`
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
LS1012A has a SEC v5.4 security engine.
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
There is a thermal monitoring unit on ls1012a soc which can
monitor and record the temperature of cores so that appropriate actions
can be taken or alarm the user when the temperature exceeds a programmed
temperature threshold.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
Updated sata node to add ecc register address and dma coherence
property.
Enable sata on ls1012a platforms as well.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
For ls1046 sata, ecc should be disabled due to a erratum.
Provide the ecc register address for driver to use.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
|
For ls1043 sata, ecc should be disabled due to a erratum.
Provide the ecc register address for driver to use.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
|
