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Added gpios and dspi to device tree.
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Signed-off-by: Xiaobo Xie <xiaobo.xie@nxp.com>
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The Ethernet nodes 0 and 1 aren't present on LS1046A RDB platforms.
Remove the nodes in order to avoid error messages at boot time.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
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The performance is impacted if the memory is mapped as non coherent.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
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Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Signed-off-by: Xiaobo Xie <xiaobo.xie@nxp.com>
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Signed-off-by: Xiaobo Xie <xiaobo.xie@nxp.com>
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Keep PCIe node in "disabled" status as SoC default.
Only enable it for boards with PCIe circuit designed,
such as LS1012ARDB and LS1012AQDS.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
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LS1012A-2G5RDB is a different design from LS1012ARDB,
but has some common SoC features. Key feature on this
board is 2.5Gbps SGMII.
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
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Add optee device tree node on ls1012a, ls1043a, ls1046a, ls1088a
and ls208xa.
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Recently logic to enable RGMII tx delay was changed by
below patch.
https://patchwork.kernel.org/patch/9447581/
Based on the patch, enabling tx delay again using rgmii-txid.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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Update ls1012a dtsi and platform dts files with
support for ppfe.
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
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Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
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Add PCIe controller node for ls1012a platform.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Add MSI controller node for ls1012a platform.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
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Add the identify of the platform to support set the rcpm with
big-endian or little-endian.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Add the identify of the platform to support set the rcpm with
big-endian or little-endian.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Add the identify of the platform to support set the rcpm with
big-endian or little-endian.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Add the identify of the platform to support set the rcpm with
big-endian or little-endian.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Add the identify of the platform to support set the rcpm with
big-endian or little-endian.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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According to PSCI standard v0.2, for CPU_SUSPEND call, which is
used by cpu idle framework, bit[16] of state parameter must be 0.
So update bit[16] of property 'arm,psci-suspend-param', which is
used as state parameter, to 0.
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
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Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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This patch adds iommu-map property for PCIe, which enables
SMMU for these devices on LS1088.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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This patch adds iommu-map property for PCIe, which enables
SMMU for these devices on LS208xA devices.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
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Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
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Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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Signed-Off-by: Guanhua Gao <guanhua.gao@nxp.com>
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Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
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Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
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LS1012A has one USB 3.0(DWC3) controller and
one USB 2.0 controller.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
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Add "dis_rxdet_inp3_quirk" bollean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
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-As per board design, different QSPI flash is connected on
boards, hence change QSPI flash node from s25fl256s1 to s25fs512ss in
device tree.
-Enable fast-read support in QSPI node.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
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Update ls2081ardb.dts for below nodes:
-As per updated board design, different QSPI flash is connected on
boards, hence change QSPI flash node from n25q512a to s25fs512ss in
device tree.
-Enable dual flash support in QSPI node.
-Add DTS node for INA220.
-Enable SATA node.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Tao Yang <b31903@freescale.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
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Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
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Modification required for fsl,dpaa node placement.
Now the node is part of soc node.
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
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Signed-off-by: Iordache Florinel-R70177 <florinel.iordache@nxp.com>
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
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Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
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LS1088AQDS consist of NOR, NAND and FPGA connected over IFC
LS1088ARDB consist of NAND and FPGA connected over IFC.
So add flash information in ifc node of device tree.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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This is temporary patch, will rewrite for open source
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
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This patch add support for NXP LS2081ARDB board which has
LS2081A SoC.
LS2081A SoC is 40-pin derivative of LS2088A SoC
So, from functional perspective both are same.
Hence,ls2088a SoC dtsi files are included from ls2081ARDB dts
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
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Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
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Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
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Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
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