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2017-12-12arm/dts: Add nodes for flexcan devices present on LS1021A-Rev2 SoCPankaj Bansal
This patch adds the device nodes for flexcan controller(s) present on LS1021A-Rev2 SoC. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Reviewed-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
2017-12-12arm: dts: Remove p1010-flexcan compatible from imx series dtsPankaj Bansal
The flexcan driver has been modified to check for big-endian dts property for be read/write to flexcan registers/mb. An exception to this rule is powerpc P1010RDB, which is always big-endian, even if big-endian is not present in dts. This is checked using p1010-flexcan compatible in dts. Therefore, remove p1010-flexcan compatible from imx series dts, as their flexcan core is little endian. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
2017-12-12dma: ls1021a: fix qdma node to dtsiWen He
Signed-off-by: Wen He <wen.he_1@nxp.com>
2017-12-12arm32: dts: ls1021a: Add a compatible node for ls1021a esdhcyinbo.zhu
The compatible node is to mark the 1021a esdhc HW feature Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
2017-12-12ARM: dts: ls1021a: Enable the esdhcyinbo.zhu
Ls1021a esdhc had been enabled in uboot, but it had not been enabled it in kernel, So set the esdhc's status to "okay". Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
2017-12-12PFE: fix compile issue on arm32Zhao Qiang
add CONFIG_FSL_PPFE_UTIL_DISABLED to arm32 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-28arm: dts: ls1021a: Add the identify of the platform to support to set rcpm bitZhang Ying-22455
Add the identify of the platform to support set the rcpm with big-endian or little-endian. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
2017-09-25arm: configs: enable CONFIG_IP_MULTICAST in lsdk.configYangbo Lu
1588 stack requires multicast communication. It's proper to enable CONFIG_IP_MULTICAST in default. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2017-09-25ARM: dts: ls1021a: Add quirk for Erratum A009116Rajesh Bhagat
Add "snps,quirk-frame-length-adjustment" property to USB3 node for erratum A009116. This property provides value of GFLADJ_30MHZ for post silicon frame length adjustment. Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-09-25ARM: DTS: Fix register map for virt-capable GICMarc Zyngier
Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25arm: multi_v7_defconfig: enable RTC_DRV_PCF2127 and RTC_DRV_PCF85263 on ↵Zhang Ying-22455
32bit system Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
2017-09-25arm:configs: Add lttng.config to support LTTng modulesShengzhou Liu
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2017-09-25arm64: dts: ls1021/ls1043/ls1046: add qdma nodesjiaheng.fan
Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
2017-09-25dts: ls1021a: update the clockgen nodeYuantian Tang
qoriq clock driver has been updated to parse the clock configuration information defined in driver itself not in dts. Since the new implementation and the bindings have been merged, it is time to update the clock related node and remove redundent clock configuration information from the dts. Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
2017-09-25config: enable support for lxd and lxd-bridgeIoana Ciornei
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
2017-09-25multi_v7_defconfig: added config options required for DPAA 1Madalin Bucur
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
2017-09-25arm: config: Remove CONFIG_MTD_CFI_BE_BYTE_SWAP in multi_v7_defconfigAlison Wang
For the patch to update struct map_info's swap field based on device characteristics defined in device tree, CONFIG_MTD_CFI_BE_BYTE_SWAP is not used. This patch will remove it in multi_v7_defconfig. Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-09-25config: arm32: enable necessary options for KVM and containersIoana Ciornei
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
2017-09-25arm: configs: Add lsdk.config for arm32 in lsdkShengzhou Liu
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2017-09-25config: multiv8: enable CONFIG_FSL_SDK_DPA insteadZhao Qiang
enable CONFIG_FSL_SDK_DPA instead of CONFIG_HAS_FSL_QBMAN for 32b os on arm64 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-25arm: add pgprot_cached and pgprot_cached_ns supportJianhua Xie
Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
2017-09-25arm: add new non-shareable ioremapPan Jiafei
Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com> Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
2017-09-25arm: dma-mapping: export arch_setup_dma_ops()Horia Geantă
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
2017-09-25usb: dts: for fix usb port faile issue on ls1021atwryinbo.zhu
Signed-off-by: yinbo zhu <yinbo.zhu@nxp.com>
2017-09-25arm: dts: Add big-endian for IFC on LS1021AAlison Wang
For the patch to update struct map_info's swap field based on device characteristics defined in device tree, big-endian parameter is added for LS1021A. Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-07-14arch: arm: add ARM specific fucntions required for ehci fsl driverZhao Qiang
Add below functions for ARM platform which are used by ehci fsl driver: 1. spin_event_timeout function 2. set/clear bits functions Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2017-07-14pci:add support aer/pme interrupts with none MSI/MSI-X/INTx modePo Liu
[arch part] On some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode. When chip support the aer/pme interrupts with none MSI/MSI-X/INTx mode, maybe there is interrupt line for aer pme etc. Search the interrupt number in the fdt file. Then fixup the dev->irq with it. Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Integrated-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-07-14arm: dts: ls1021a: correct the register range of dcfgZhang Ying-22455
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
2017-07-14USB3/DWC3: Add property "snps,dma-snooping" to enable snoopingChangming Huang
Some DWC3 platform has DMA snooping feature. Therefore, add property "snps,dma-snooping" to enable it. Signed-off-by: Changming Huang <jerry.huang@nxp.com>
2017-07-14USB3: DWC3: Add property snps incr burst type adjustment for INCR burst typeChangming Huang
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
2017-07-14arm: dts: ls1021a: add ftm0 nodeWang Dongsheng
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
2017-07-14dts/ls1021a-twr: optimize fast-mode to quad modeYunhui Cui
The field "m25p,fast-read" means that flash works at fast-read mode. Now Quad read mode is supported, So we remove the field, and the quad read mode is enabled by default. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
2017-07-14dts: ls1021a: Add the DTS for QSPI supportAlison Wang
This patch adds dts nodes for QSPI on LS1021A. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-07-14arm/dts-ls1021: add pcie aer/pme interrupt-name property in the dtsPo Liu
NXP arm aer/pme interrupts was not MSI/MSI-X/INTx but using interrupt line independently. This patch add a "aer" "pme" interrupt-names for aer/pme interrupts. With the interrupt-names "aer","pme" code could probe aer/pme interrupt line for pcie root port, replace the aer/pme interrupt service irqs. This patch is intend to fixup the Layerscape platforms which aer/pme interrupt was not MSI/MSI-X/INTx, but using interrupt line independently. Since the interrupt-names "intr" never been used. Remove it. Signed-off-by: Po Liu <po.liu@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-07-14arm: dts: ls1021a: share all MSIsMinghuan Lian
In order to maximize the use of MSI, a PCIe controller will share all MSI controllers. The patch changes msi-parent to refer to all MSI controller dts nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-07-14arm: dts: ls1021a: fix typo of MSI compatible stringMinghuan Lian
"1" should be replaced by "l". This is a typo. The patch is to fix it. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2017-07-14arm: defconfig: enable CONFIG_FTM_ALARM on 32bit systemZhang Ying-22455
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
2017-07-14arm: multi_v7_defconfig: support built-in eSDHCYangbo Lu
This patch is to support eSDHC compile with built-in mode instead of module mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
2017-07-14ARM: multi_v7_defconfig: Enable some MTD options for FSL_IFCAlison Wang
Enable some MTD options for FSL_IFC driver, such as CONFIG_MTD_CFI_BE_BYTE_SWAP, CONFIG_MTD_CFI_AMDSTD and CONFIG_MTD_PHYSMAP_OF. Signed-off-by: Alison Wang <alison.wang@nxp.com>
2017-07-14arm: config: update config for lsdkShengzhou Liu
- update multi_v7_defconfig - add multi_v7_lpae.config - add multi_v8.config Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
2017-06-24mm: larger stack guard gap, between vmasHugh Dickins
commit 1be7107fbe18eed3e319a6c3e83c78254b693acb upstream. Stack guard page is a useful feature to reduce a risk of stack smashing into a different mapping. We have been using a single page gap which is sufficient to prevent having stack adjacent to a different mapping. But this seems to be insufficient in the light of the stack usage in userspace. E.g. glibc uses as large as 64kB alloca() in many commonly used functions. Others use constructs liks gid_t buffer[NGROUPS_MAX] which is 256kB or stack strings with MAX_ARG_STRLEN. This will become especially dangerous for suid binaries and the default no limit for the stack size limit because those applications can be tricked to consume a large portion of the stack and a single glibc call could jump over the guard page. These attacks are not theoretical, unfortunatelly. Make those attacks less probable by increasing the stack guard gap to 1MB (on systems with 4k pages; but make it depend on the page size because systems with larger base pages might cap stack allocations in the PAGE_SIZE units) which should cover larger alloca() and VLA stack allocations. It is obviously not a full fix because the problem is somehow inherent, but it should reduce attack space a lot. One could argue that the gap size should be configurable from userspace, but that can be done later when somebody finds that the new 1MB is wrong for some special case applications. For now, add a kernel command line option (stack_guard_gap) to specify the stack gap size (in page units). Implementation wise, first delete all the old code for stack guard page: because although we could get away with accounting one extra page in a stack vma, accounting a larger gap can break userspace - case in point, a program run with "ulimit -S -v 20000" failed when the 1MB gap was counted for RLIMIT_AS; similar problems could come with RLIMIT_MLOCK and strict non-overcommit mode. Instead of keeping gap inside the stack vma, maintain the stack guard gap as a gap between vmas: using vm_start_gap() in place of vm_start (or vm_end_gap() in place of vm_end if VM_GROWSUP) in just those few places which need to respect the gap - mainly arch_get_unmapped_area(), and and the vma tree's subtree_gap support for that. Original-patch-by: Oleg Nesterov <oleg@redhat.com> Original-patch-by: Michal Hocko <mhocko@suse.com> Signed-off-by: Hugh Dickins <hughd@google.com> Acked-by: Michal Hocko <mhocko@suse.com> Tested-by: Helge Deller <deller@gmx.de> # parisc Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> [wt: backport to 4.11: adjust context] [wt: backport to 4.9: adjust context ; kernel doc was not in admin-guide] Signed-off-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-06-17ARM: defconfigs: make NF_CT_PROTO_SCTP and NF_CT_PROTO_UDPLITE built-inArnd Bergmann
[ Upstream commit 5aff1d245e8cc1ab5c4517d916edaed9e3f7f973 ] The symbols can no longer be used as loadable modules, leading to a harmless Kconfig warning: arch/arm/configs/imote2_defconfig:60:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE arch/arm/configs/imote2_defconfig:59:warning: symbol value 'm' invalid for NF_CT_PROTO_SCTP arch/arm/configs/ezx_defconfig:68:warning: symbol value 'm' invalid for NF_CT_PROTO_UDPLITE arch/arm/configs/ezx_defconfig:67:warning: symbol value 'm' invalid for NF_CT_PROTO_SCTP Let's make them built-in. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Sasha Levin <alexander.levin@verizon.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-06-14ARM: 8637/1: Adjust memory boundaries after reservationsLaura Abbott
commit 985626564eedc470ce2866e53938303368ad41b7 upstream. adjust_lowmem_bounds is responsible for setting up the boundary for lowmem/highmem. This needs to be setup before memblock reservations can occur. At the time memblock reservations can occur, memory can also be removed from the system. The lowmem/highmem boundary and end of memory may be affected by this but it is currently not recalculated. On some systems this may be harmless, on others this may result in incorrect ranges being passed to the main memory allocator. Correct this by recalculating the lowmem/highmem boundary after all reservations have been made. Tested-by: Magnus Lilja <lilja.magnus@gmail.com> Signed-off-by: Laura Abbott <labbott@redhat.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Julien Grall <julien.grall@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-06-14ARM: 8636/1: Cleanup sanity_check_meminfoLaura Abbott
commit 374d446d25d6271ee615952a3b7f123ba4983c35 upstream. The logic for sanity_check_meminfo has become difficult to follow. Clean up the code so it's more obvious what the code is actually trying to do. Additionally, meminfo is now removed so rename the function to better describe its purpose. Tested-by: Magnus Lilja <lilja.magnus@gmail.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Laura Abbott <lauraa@codeaurora.org> Signed-off-by: Laura Abbott <labbott@redhat.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Julien Grall <julien.grall@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-06-14KVM: arm/arm64: Handle possible NULL stage2 pud when ageing pagesMarc Zyngier
commit d6dbdd3c8558cad3b6d74cc357b408622d122331 upstream. Under memory pressure, we start ageing pages, which amounts to parsing the page tables. Since we don't want to allocate any extra level, we pass NULL for our private allocation cache. Which means that stage2_get_pud() is allowed to fail. This results in the following splat: [ 1520.409577] Unable to handle kernel NULL pointer dereference at virtual address 00000008 [ 1520.417741] pgd = ffff810f52fef000 [ 1520.421201] [00000008] *pgd=0000010f636c5003, *pud=0000010f56f48003, *pmd=0000000000000000 [ 1520.429546] Internal error: Oops: 96000006 [#1] PREEMPT SMP [ 1520.435156] Modules linked in: [ 1520.438246] CPU: 15 PID: 53550 Comm: qemu-system-aar Tainted: G W 4.12.0-rc4-00027-g1885c397eaec #7205 [ 1520.448705] Hardware name: FOXCONN R2-1221R-A4/C2U4N_MB, BIOS G31FB12A 10/26/2016 [ 1520.463726] task: ffff800ac5fb4e00 task.stack: ffff800ce04e0000 [ 1520.469666] PC is at stage2_get_pmd+0x34/0x110 [ 1520.474119] LR is at kvm_age_hva_handler+0x44/0xf0 [ 1520.478917] pc : [<ffff0000080b137c>] lr : [<ffff0000080b149c>] pstate: 40000145 [ 1520.486325] sp : ffff800ce04e33d0 [ 1520.489644] x29: ffff800ce04e33d0 x28: 0000000ffff40064 [ 1520.494967] x27: 0000ffff27e00000 x26: 0000000000000000 [ 1520.500289] x25: ffff81051ba65008 x24: 0000ffff40065000 [ 1520.505618] x23: 0000ffff40064000 x22: 0000000000000000 [ 1520.510947] x21: ffff810f52b20000 x20: 0000000000000000 [ 1520.516274] x19: 0000000058264000 x18: 0000000000000000 [ 1520.521603] x17: 0000ffffa6fe7438 x16: ffff000008278b70 [ 1520.526940] x15: 000028ccd8000000 x14: 0000000000000008 [ 1520.532264] x13: ffff7e0018298000 x12: 0000000000000002 [ 1520.537582] x11: ffff000009241b93 x10: 0000000000000940 [ 1520.542908] x9 : ffff0000092ef800 x8 : 0000000000000200 [ 1520.548229] x7 : ffff800ce04e36a8 x6 : 0000000000000000 [ 1520.553552] x5 : 0000000000000001 x4 : 0000000000000000 [ 1520.558873] x3 : 0000000000000000 x2 : 0000000000000008 [ 1520.571696] x1 : ffff000008fd5000 x0 : ffff0000080b149c [ 1520.577039] Process qemu-system-aar (pid: 53550, stack limit = 0xffff800ce04e0000) [...] [ 1521.510735] [<ffff0000080b137c>] stage2_get_pmd+0x34/0x110 [ 1521.516221] [<ffff0000080b149c>] kvm_age_hva_handler+0x44/0xf0 [ 1521.522054] [<ffff0000080b0610>] handle_hva_to_gpa+0xb8/0xe8 [ 1521.527716] [<ffff0000080b3434>] kvm_age_hva+0x44/0xf0 [ 1521.532854] [<ffff0000080a58b0>] kvm_mmu_notifier_clear_flush_young+0x70/0xc0 [ 1521.539992] [<ffff000008238378>] __mmu_notifier_clear_flush_young+0x88/0xd0 [ 1521.546958] [<ffff00000821eca0>] page_referenced_one+0xf0/0x188 [ 1521.552881] [<ffff00000821f36c>] rmap_walk_anon+0xec/0x250 [ 1521.558370] [<ffff000008220f78>] rmap_walk+0x78/0xa0 [ 1521.563337] [<ffff000008221104>] page_referenced+0x164/0x180 [ 1521.569002] [<ffff0000081f1af0>] shrink_active_list+0x178/0x3b8 [ 1521.574922] [<ffff0000081f2058>] shrink_node_memcg+0x328/0x600 [ 1521.580758] [<ffff0000081f23f4>] shrink_node+0xc4/0x328 [ 1521.585986] [<ffff0000081f2718>] do_try_to_free_pages+0xc0/0x340 [ 1521.592000] [<ffff0000081f2a64>] try_to_free_pages+0xcc/0x240 [...] The trivial fix is to handle this NULL pud value early, rather than dereferencing it blindly. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-06-14arm: KVM: Allow unaligned accesses at HYPMarc Zyngier
commit 33b5c38852b29736f3b472dd095c9a18ec22746f upstream. We currently have the HSCTLR.A bit set, trapping unaligned accesses at HYP, but we're not really prepared to deal with it. Since the rest of the kernel is pretty happy about that, let's follow its example and set HSCTLR.A to zero. Modern CPUs don't really care. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Christoffer Dall <cdall@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-05-25ARM: dts: imx6sx-sdb: Remove OPP overrideLeonard Crestez
commit d8581c7c8be172dac156a19d261f988a72ce596f upstream. The board file for imx6sx-sdb overrides cpufreq operating points to use higher voltages. This is done because the board has a shared rail for VDD_ARM_IN and VDD_SOC_IN and when using LDO bypass the shared voltage needs to be a value suitable for both ARM and SOC. This only applies to LDO bypass mode, a feature not present in upstream. When LDOs are enabled the effect is to use higher voltages than necessary for no good reason. Setting these higher voltages can make some boards fail to boot with ugly semi-random crashes reminiscent of memory corruption. These failures only happen on board rev. C, rev. B is reported to still work. Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> Fixes: 54183bd7f766 ("ARM: imx6sx-sdb: add revb board and make it default") Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-05-25ARM: dts: at91: sama5d3_xplained: not all ADC channels are availableLudovic Desroches
commit d3df1ec06353e51fc44563d2e7e18d42811af290 upstream. Remove ADC channels that are not available by default on the sama5d3_xplained board (resistor not populated) in order to not create confusion. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-05-25ARM: dts: at91: sama5d3_xplained: fix ADC vrefLudovic Desroches
commit 9cdd31e5913c1f86dce7e201b086155b3f24896b upstream. The voltage reference for the ADC is not 3V but 3.3V since it is connected to VDDANA. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2017-05-25ARM: 8670/1: V7M: Do not corrupt vector table around v7m_invalidate_l1 callVladimir Murzin
commit 6d80594936914e798b1b54b3bfe4bd68d8418966 upstream. We save/restore registers around v7m_invalidate_l1 to address pointed by r12, which is vector table, so the first eight entries are overwritten with a garbage. We already have stack setup at that stage, so use it to save/restore register. Fixes: 6a8146f420be ("ARM: 8609/1: V7M: Add support for the Cortex-M7 processor") Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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