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2014-11-24irqchip: mips-gic: Support local interruptsAndrew Bresticker
The MIPS GIC supports 7 local interrupts, 2 of which are the GIC local watchdog and count/compare timer. The remainder are CPU interrupts which may optionally be re-routed through the GIC. GIC hardware IRQs 0-6 are now used for local interrupts while hardware IRQs 7+ are used for external (shared) interrupts. Note that the 5 CPU interrupts may not be re-routable through the GIC. In that case mapping will fail and the vectors reported in C0_IntCtl should be used instead. gic_get_c0_compare_int() and gic_get_c0_perfcount_int() will return the correct IRQ number to use for the C0 timer and perfcounter interrupts based on the routability of those interrupts through the GIC. A separate irq_chip, with callbacks that mask/unmask the local interrupt on all CPUs, is used for the C0 timer and performance counter interrupts since all other platforms do not use the percpu IRQ API for those interrupts. Malta, SEAD-3, and the GIC clockevent driver have been updated to use local interrupts and the R4K clockevent driver has been updated to poll for C0 timer interrupts through the GIC when the GIC is present. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7819/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24irqchip: mips-gic: Use separate edge/level irq_chipsAndrew Bresticker
GIC edge-triggered interrupts must be acknowledged by clearing the edge detector via a write to GIC_SH_WEDGE. Create a separate edge-triggered irq_chip with the appropriate irq_ack() callback. This also allows us to get rid of gic_irq_flags. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7818/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24irqchip: mips-gic: Probe for number of external interruptsAndrew Bresticker
Instead of requiring platforms to define the correct GIC_NUM_INTRS, use the value reported in GIC_SH_CONFIG. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7817/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24irqchip: mips-gic: Stop using per-platform mapping tablesAndrew Bresticker
Now that the GIC properly uses IRQ domains, kill off the per-platform routing tables that were used to make the GIC appear transparent. This includes: - removing the mapping tables and the support for applying them, - moving GIC IPI support to the GIC driver, - properly routing the i8259 through the GIC on Malta, and - updating IRQ assignments on SEAD-3 when the GIC is present. Platforms no longer will pass an interrupt mapping table to gic_init. Instead, they will pass the CPU interrupt vector (2 - 7) that they expect the GIC to route interrupts to. Note that in EIC mode this value is ignored and all GIC interrupts are routed to EIC vector 1. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7816/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24irqchip: mips-gic: Use IRQ domainsAndrew Bresticker
Use a simple IRQ domain for the MIPS GIC. Remove the gic_platform_init callback as it's no longer necessary for it to set the irqchip. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7811/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24irqchip: mips-gic: Implement irq_set_type callbackAndrew Bresticker
Implement an irq_set_type callback for the GIC which is used to set the polarity and trigger type of GIC interrupts. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7810/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24irqchip: mips-gic: Remove platform irq_ack/irq_eoi callbacksAndrew Bresticker
There's no need for platforms to have their own GIC irq_ack/irq_eoi callbacks. irq_ack need only clear the GIC's edge detector on edge-triggered interrupts and there's no need at all for irq_eoi. Also get rid of the mask_ack callback since it's not necessary either. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7809/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: Move GIC to drivers/irqchip/Andrew Bresticker
Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Jason Cooper <jason@lakedaemon.net> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7812/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: Move MIPS_GIC_IRQ_BASE into platform irq.hAndrew Bresticker
Define a generic MIPS_GIC_IRQ_BASE which should be suitable for all current boards in <mach-generic/irq.h>. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7808/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: Malta: Move MSC01 interrupt baseAndrew Bresticker
The GIC on Malta boards supports a total of 47 interrupts (40 shared and 7 local) and is assigned a base of 24. This overlaps with the MSC01 interrupt assignments which have a base of 64, so move the MSC01 interrupt base back a bit to give the GIC some room. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7815/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: sead3: Do not overlap CPU/GIC IRQ rangesAndrew Bresticker
In preparation for GIC IRQ domain support, assign a GIC IRQ base that does not overlap with the CPU IRQs. Note that this breaks SEAD-3 when the GIC is in EIC mode, though I'm not convinced it was working before either. It will be fixed in the following patches. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7813/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: SEAD3: Remove sead3-serial.cAndrew Bresticker
It's a duplicate of sead3-platform.c and is not even compiled. Remove it before we start fixing up IRQ assignments. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7807/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: Remove gic_{enable,disable}_interrupt()Andrew Bresticker
Nothing calls gic_{enable,disable}_interrupt() any more. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7806/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: smp-cps: Enable all hardware interrupts on secondary CPUsAndrew Bresticker
Currently interrupt vectors 2 and 5 are left disabled on secondary CPUs. Since systems using CPS must also have a GIC, which is responsible for routing all external interrupts and can map them to any hardware interrupt vector, enable the remaining vectors. The two software interrupt vectors are left disabled since they are not used with CPS. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7803/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: Add hook to get C0 performance counter interruptAndrew Bresticker
The hardware perf event driver and oprofile interpret the global cp0_perfcount_irq differently: in the hardware perf event driver it is an offset from MIPS_CPU_IRQ_BASE and in oprofile it is the actual IRQ number. This still works most of the time since MIPS_CPU_IRQ_BASE is usually 0, but is clearly wrong. Since the performance counter interrupt may vary from platform to platform like the C0 timer interrupt, add the optional get_c0_perfcount_int hook which returns the IRQ number of the performance counter. The hook should return < 0 if the performance counter interrupt is shared with the timer. If the hook is not present, the CPU vector reported in C0_IntCtl (cp0_perfcount_irq) is used. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7805/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: i8259: Use IRQ domainsAndrew Bresticker
Create a legacy IRQ domain for the 16 i8259 interrupts. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7804/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: Set vint handler when mapping CPU interruptsAndrew Bresticker
When mapping an interrupt in the CPU IRQ domain, set the vint handler for that interrupt if the CPU uses vectored interrupt handling. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7802/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: Provide a generic plat_irq_dispatchAndrew Bresticker
For platforms which boot with device-tree or have correctly chained all external interrupt controllers, a generic plat_irq_dispatch() can be used. Implement a plat_irq_dispatch() which simply handles all the pending interrupts as reported by C0_Cause. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7801/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: Rename mips_cpu_intc_init() -> mips_cpu_irq_of_init()Andrew Bresticker
mips_cpu_intc_init() is used for DT-based initialization of the CPU IRQ domain. Give it a more appropriate name. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7800/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: Always use IRQ domains for CPU IRQsAndrew Bresticker
Use an IRQ domain for the 8 CPU IRQs in both the DT and non-DT cases. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-by: Qais Yousef <qais.yousef@imgtec.com> Tested-by: Qais Yousef <qais.yousef@imgtec.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Jeffrey Deans <jeffrey.deans@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Jonas Gorski <jogo@openwrt.org> Cc: John Crispin <blogic@openwrt.org> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7799/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: cpu: Add 'noftlb' kernel command line option to disable the FTLBMarkos Chandras
Add new 'noftlb' kernel command line option to disable the FTLB. Since the kernel command line is not available when probing and enabling the CPU features in cpu_probe(), we let the kernel configure the FTLB during the config4 decode operation and we disable the FTLB later on, once the command line has become available to us. This should have no negative effects since FTLB isn't used so early in the boot process. FTLB increases the effective TLB size leading to less TLB misses. However, sometimes it's useful to be able to disable it when debugging memory related core features or other hardware components. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/7586/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24mips: Convert pr_warning to pr_warnJoe Perches
Use the much more common pr_warn instead of pr_warning with the goal of removing pr_warning eventually. Other miscellanea: o Coalesce formats o Realign arguments Signed-off-by: Joe Perches <joe@perches.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: LKML <linux-kernel@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/7935/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: pci-rt3883: Remove odd locking in PCI config space access codeSergey Ryazanov
Caller (generic PCI code) already do proper locking so no need to add another one here. Local PCI read/write functions are never called simultaneously, also they do not require synchronization with the PCI controller ops, since they are used before the controller registration. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Cc: Gabor Juhos <juhosg@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/7603/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: pci-ar7{1x, 24}x: remove odd locking in PCI config space access codeSergey Ryazanov
Caller (generic PCI code) already do proper locking so no need to add another one here. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Cc: Gabor Juhos <juhosg@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/7602/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: MSP71xx: remove odd locking in PCI config space access codeSergey Ryazanov
Caller (generic PCI code) already do proper locking so no need to add another one here. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7601/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: NILE4: Remove odd locking in PCI config space access codeSergey Ryazanov
Caller (generic PCI code) already do proper locking so no need to add another one here. Signed-off-by: Sergey Ryazanov <ryazanov.s.a@gmail.com> Cc: Linux MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7600/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24MIPS: Add arch_trigger_all_cpu_backtrace() functionEunbong Song
Currently, arch_trigger_all_cpu_backtrace() is defined in only x86 and sparc which have an NMI. But in case of softlockup, it could be possible to dump backtrace of all cpus. and this could be helpful for debugging. for example, if system has 2 cpus. CPU 0 CPU 1 acquire read_lock() try to do write_lock() ,,, missing read_unlock() In this case, softlockup will occur becasuse CPU 0 does not call read_unlock(). And dump_stack() print only backtrace for "CPU 0". If CPU1's backtrace is printed it's very helpful. [ralf@linux-mips.org: Fixed whitespace and formatting issues.] Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8200/
2014-11-24MIPS: Remove useless parenthesesRalf Baechle
Based on the spatch @@ expression e; @@ - return (e); + return e; with heavy hand editing because some of the changes are either whitespace or identation only or result in excessivly long lines. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: jump_label.c: Handle the microMIPS J instruction encodingMaciej W. Rozycki
Implement the microMIPS encoding of the J instruction for the purpose of the static keys feature, fixing a crash early on in bootstrap as the kernel is unhappy seeing the ISA bit set in jump table entries. Make sure the ISA bit correctly reflects the instruction encoding chosen for the kernel, 0 for the standard MIPS and 1 for the microMIPS encoding. Also make sure the instruction to patch is a 32-bit NOP in the microMIPS mode as by default the 16-bit short encoding is assumed Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8516/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: jump_label.c: Correct the span of the J instructionMaciej W. Rozycki
Correct the check for the span of the 256MB segment addressable by the J instruction according to this instruction's semantics. The calculation of the jump target is applied to the address of the delay-slot instruction that immediately follows. Adjust the check accordingly by adding 4 to `e->code' that holds the address of the J instruction itself. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8515/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: Zero variable read by get_user / __get_user in case of an error.Ralf Baechle
This wasn't happening in all cases. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: lib: memcpy: Restore NOP on delay slot before returning to callerMarkos Chandras
Commit cf62a8b8134dd3 ("MIPS: lib: memcpy: Use macro to build the copy_user code") switched to a macro in order to build the memcpy symbols in preparation for the EVA support. However, this commit also removed the NOP instruction after the 'jr ra' when returning back to the caller. This had no visible side-effects since the next instruction was a load to the t0 register which was already in the clobbered list, but it may have undesired effects in the future if some other code is introduced in between the .Ldone and the .Ll_exc_copy labels. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # v3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8512/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: tlb-r4k: Add missing HTW stop/start sequencesMarkos Chandras
HTW needs to stop and start again whenever the EntryHI register changes otherwise an inflight HTW operation might use the new EntryHI register for updating an old entry and that could lead to crashes or even a machine check exception. We fix this by ensuring the HTW has stop whenever the EntryHI register is about to change Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # v3.17+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8511/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: asm: uaccess: Add v1 register to clobber list on EVAMarkos Chandras
When EVA is turned on and prefetching is being used in memcpy.S, the v1 register is being used as a helper register to the PREFE instruction. However, v1 ($3) was not in the clobber list, which means that the compiler did not preserve it across function calls, and that could corrupt the value of the register leading to all sorts of userland crashes. We fix this problem by using the DADDI_SCRATCH macro to define the clobbered register when CONFIG_EVA && CONFIG_CPU_HAS_PREFETCH are enabled. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: <stable@vger.kernel.org> # v3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8510/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: oprofile: Fix backtrace on 64-bit kernelAaro Koskinen
Fix incorrect cast that always results in wrong address for the new frame on 64-bit kernels. Signed-off-by: Aaro Koskinen <aaro.koskinen@nsn.com> Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8110/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: Loongson: Set Loongson-3's ISA level to MIPS64R1Huacai Chen
In CPU manual Loongson-3 is MIPS64R2 compatible, but during tests we found that its EI/DI instructions have problems. So we just set the ISA level to MIPS64R1. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/8320/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: Loongson: Fix the write-combine CCA value settingHuacai Chen
All Loongson-2/3 processors support _CACHE_UNCACHED_ACCELERATED, not only Loongson-3A. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/8319/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: IP27: Fix __node_distances undefined errorJames Cowgill
export the __node_distances symbol in the ip27 memory code to fix the build error: Building modules, stage 2. MODPOST 311 modules ERROR: "__node_distances" [drivers/block/nvme.ko] undefined! scripts/Makefile.modpost:90: recipe for target '__modpost' failed when building the kernel with: CONFIG_SGI_IP27=y CONFIG_BLK_DEV_NVME=m Signed-off-by: James Cowgill <James.Cowgill@imgtec.com> Cc: <stable@vger.kernel.org> # v3.15+ Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-19MIPS: Loongson3: Fix __node_distances undefined errorJames Cowgill
export the __node_distances symbol in the loongson3 numa code to fix the build error: Building modules, stage 2. MODPOST 221 modules ERROR: "__node_distances" [drivers/block/nvme.ko] undefined! scripts/Makefile.modpost:90: recipe for target '__modpost' failed when building the kernel with: CONFIG_CPU_LOONGSON3=y CONFIG_NUMA=y CONFIG_BLK_DEV_NVME=m Signed-off-by: James Cowgill <James.Cowgill@imgtec.com> Cc: <stable@vger.kernel.org> # v3.17+ Reviewed-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Huacai Chen <chenhc@lemote.com> Cc: linux-mips@linux-mips.org Cc: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Patchwork: https://patchwork.linux-mips.org/patch/8444/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-07MIPS: Fix build with binutils 2.24.51+Manuel Lauss
Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-06MIPS: R3000: Fix debug output for Virtual page numberIsamu Mogi
Virtual page number of R3000 in entryhi is 20 bit from MSB. But in dump_tlb(), the bit mask to read it from entryhi is 19 bit (0xffffe000). The patch fixes that to 0xfffff000. Signed-off-by: Isamu Mogi <isamu@leafytree.jp> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8290/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-04MIPS: Fix strnlen_user() return value in case of overlong strings.Ralf Baechle
We were returning maxlen like the userland strnlen if no '\0' character was encountered while the kernel version is expected to return a value larger than maxlen. Fixed to return maxlen + 1. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-29MIPS: CMA: Do not reserve memory if not requiredZubair Lutfullah Kakakhel
Even if CMA is disabled, the for_each_memblock macro expands to run reserve_bootmem once. Hence, reserve_bootmem attempts to reserve location 0 of size 0. Add a check to avoid that. Issue was highlighted during testing with EVA enabled. resrve_bootmem used to exit gracefully when passed arguments to reserve 0 size location at 0 without EVA. But with EVA enabled, macros would point to different addresses and the code would trigger a BUG. Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Tested-by: Markos Chandras <markos.chandras@imgtec.com> Tested-by: Huacai Chen <chenhc@lemote.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8231/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-27MIPS: Wire up bpf syscall.Ralf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-27MIPS/Xlp: Remove the dead function destroy_irq() to fix build errorYijing Wang
Commit 465665f78a7 ("mips: Kill pointless destroy_irq()") removed the destroy_irq(). So remove the leftover one in xlp_setup_msix() to fix build error. arch/mips/pci/msi-xlp.c: In function 'xlp_setup_msix': arch/mips/pci/msi-xlp.c:447:3: error: implicit declaration of function 'destroy_irq'.. cc1: some warnings being treated as errors make[1]: *** [arch/mips/pci/msi-xlp.o] Error 1 make: *** [arch/mips/pci/] Error 2 Signed-off-by: Yijing Wang <wangyijing@huawei.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: Xinwei Hu <huxinwei@huawei.com> Cc: Wuyun <wuyun.wu@huawei.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Russell King <linux@arm.linux.org.uk> Cc: linux-arch@vger.kernel.org Cc: arnab.basu@freescale.com Cc: Bharat.Bhushan@freescale.com Cc: x86@kernel.org Cc: Arnd Bergmann <arnd@arndb.de> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: xen-devel@lists.xenproject.org Cc: Joerg Roedel <joro@8bytes.org> Cc: iommu@lists.linux-foundation.org Cc: linux-mips@linux-mips.org Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-s390@vger.kernel.org Cc: Sebastian Ott <sebott@linux.vnet.ibm.com> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-ia64@vger.kernel.org Cc: David S. Miller <davem@davemloft.net> Cc: sparclinux@vger.kernel.org Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: David Vrabel <david.vrabel@citrix.com> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Liviu Dudau <liviu@dudau.co.uk> Patchwork: https://patchwork.linux-mips.org/patch/8087/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-27MIPS: Octeon: Make Octeon GPIO IRQ chip CPU hotplug-awareAlexander Sverdlin
Make Octeon GPIO IRQ chip CPU hotplug-aware Seems that irq_cpu_offline callbacks were forgotten in v1 and v2 CIU GPIO chips. There is such a callback for octeon_irq_chip_ciu2_gpio, covering CIU2 chips. Without this callback GPIO IRQs are not being migrated during core offlining. Patch is tested on Octeon II. Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nsn.com> Cc: David Daney <ddaney.cavm@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8201/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-24MIPS: SEAD3: Fix I2C device registration.Ralf Baechle
This isn't a module and shouldn't be one. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-24MIPS: SEAD3: Nuke PIC32 I2C driver.Ralf Baechle
A platform driver for which nothing ever registers the corresponding platform device. Also it was driving the same hardware as sead3-i2c-drv.c so redundant anyway and couldn't co-exist with that driver because each of them was using a private spinlock to protect access to the same hardware resources. This also fixes a randconfig problem: arch/mips/mti-sead3/sead3-pic32-i2c-drv.c: In function 'i2c_platform_probe': arch/mips/mti-sead3/sead3-pic32-i2c-drv.c:345:2: error: implicit declaration of function 'i2c_add_numbered_adapter' [-Werror=implicit-function-declaration] ret = i2c_add_numbered_adapter(&priv->adap); ^ arch/mips/mti-sead3/sead3-pic32-i2c-drv.c: In function 'i2c_platform_remove': arch/mips/mti-sead3/sead3-pic32-i2c-drv.c:361:2: error: implicit declaration of function 'i2c_del_adapter' [-Werror=implicit-function-declaration] i2c_del_adapter(&priv->adap); Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-24MIPS: ftrace: Fix a microMIPS build problemMarkos Chandras
Code before the .fixup section needs to have the .insn directive. This has no side effects on MIPS32/64 but it affects the way microMIPS loads the address for the return label. Fixes the following build problem: mips-linux-gnu-ld: arch/mips/built-in.o: .fixup+0x4a0: Unsupported jump between ISA modes; consider recompiling with interlinking enabled. mips-linux-gnu-ld: final link failed: Bad value Makefile:819: recipe for target 'vmlinux' failed The fix is similar to 1658f914ff91c3bf ("MIPS: microMIPS: Disable LL/SC and fix linker bug.") Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Cc: stable@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8117/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-10-24MIPS: MSP71xx: Fix build errorStefan Hengelein
When CONFIG_MIPS_MT_SMP is enabled, the following compilation error occurs: arch/mips/pmcs-msp71xx/msp_irq_cic.c:134: error: ‘irq’ undeclared This code clearly never saw a compiler. The surrounding code suggests, that 'd->irq' was intended, not 'irq'. This error was found with vampyr. Signed-off-by: Stefan Hengelein <stefan.hengelein@fau.de> Fixes: d7881fbdf866d7d0 ("MIPS: msp71xx: Convert to new irq_chip functions") Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8116/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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