| Age | Commit message (Expand) | Author |
|---|
| 2014-10-20 | x86, amd_nb: Add device IDs to NB tables for F15h M60h | Aravind Gopalakrishnan |
| 2014-04-01 | Merge tag 'edac_for_3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp | Linus Torvalds |
| 2014-02-27 | amd64_edac: Add support for newer F16h models | Aravind Gopalakrishnan |
| 2014-01-25 | x86/AMD/NB: Fix amd_set_subcaches() parameter type | Dan Carpenter |
| 2013-08-12 | x86, amd_nb: Clarify F15h, model 30h GART and L3 support | Aravind Gopalakrishnan |
| 2013-04-30 | Merge branch 'x86-ras-for-linus' of git://git.kernel.org/pub/scm/linux/kernel... | Linus Torvalds |
| 2013-04-19 | amd64_edac: Add Family 16h support | Aravind Gopalakrishnan |
| 2013-03-11 | x86: Constify a few items | Jan Beulich |
| 2012-07-22 | Merge branch 'x86-mce-for-linus' of git://git.kernel.org/pub/scm/linux/kernel... | Linus Torvalds |
| 2012-06-07 | x86, amd_nb: Export model 0x10 and later PCI id | Borislav Petkov |
| 2012-06-06 | x86/debug: Add KERN_<LEVEL> to bare printks, convert printks to pr_<level> | Joe Perches |
| 2012-01-12 | Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jb... | Linus Torvalds |
| 2012-01-06 | x86/PCI: amd: factor out MMCONFIG discovery | Bjorn Helgaas |
| 2011-12-21 | x86: Simplify code by removing a !SMP #ifdefs from 'struct cpuinfo_x86' | Kevin Winchester |
| 2011-03-31 | x86, amd-nb: Rename CPU PCI id define for F4 | Borislav Petkov |
| 2011-03-18 | Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp | Linus Torvalds |
| 2011-03-17 | PCI: Rename CPU PCI id define | Borislav Petkov |
| 2011-03-03 | x86, amd-nb: Misc cleanliness fixes | Borislav Petkov |
| 2011-02-10 | x86: Adjust section placement in AMD northbridge related code | Jan Beulich |
| 2011-02-07 | x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs | Hans Rosenfeld |
| 2011-01-26 | x86, amd: Extend AMD northbridge caching code to support "Link Control" devices | Hans Rosenfeld |
| 2011-01-26 | x86, amd: Enable L3 cache index disable on family 0x15 | Hans Rosenfeld |
| 2011-01-11 | x86: Use PCI method for enabling AMD extended config space before MSR method | Jan Beulich |
| 2010-11-18 | x86, cacheinfo: Cleanup L3 cache index disable support | Hans Rosenfeld |
| 2010-11-18 | x86, amd-nb: Cleanup AMD northbridge caching code | Hans Rosenfeld |
| 2010-11-18 | x86, amd-nb: Complete the rename of AMD NB and related code | Hans Rosenfeld |
| 2010-10-01 | x86, amd_nb: Enable GART support for AMD family 0x15 CPUs | Andreas Herrmann |
| 2010-09-20 | x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB | Andreas Herrmann |
