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path: root/drivers/clk/mediatek
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2015-10-01clk: mediatek: Add USB clock support in MT8173 APMIXEDSYSJames Liao
Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock is needed by USB 3.0. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: Add subsystem clocks of MT8173James Liao
Most multimedia subsystem clocks will be accessed by multiple drivers, so it's a better way to manage these clocks in CCF. This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT subsystems. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: Fix rate and dependency of MT8173 clocksJames Liao
Remove the dependency from clk_null, and give all root clocks a typical rate, include clkph_mck_o, usb_syspll_125m and hdmitx_dig_cts. dpi_ck was removed due to no clock reference to it. Replace parent clock of infra_cpum with cpum_ck, which is an external clock and can be defined in the device tree. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: Add fixed clocks support for Mediatek SoC.James Liao
This patch adds fixed clocks support by using CCF fixed-rate clock implementation. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: Add __initdata and __init for data and functionsJames Liao
Add __init for clock registration functions, and add __initdata for mtk_gate_regs initial structures. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: Remove unused code from MT8173.James Liao
Remove unused header files from MT8173, and remove unused keywords from function declaration. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: Removed unused dpi_ck clock from MT8173James Liao
The dpi_ck clock can be removed because it not actually used in topckgen and subsystems. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
2015-10-01clk: mediatek: add 13mhz clock for MT8173Joe.C
Add 13mhz clock used by GPT timer in infracfg. Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
2015-07-28Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd
* cleanup-clk-h-includes: (62 commits) clk: Remove clk.h from clk-provider.h clk: h8300: Remove clk.h and clkdev.h includes clk: at91: Include clk.h and slab.h clk: ti: Switch clk-provider.h include to clk.h clk: pistachio: Include clk.h clk: ingenic: Include clk.h clk: si570: Include clk.h clk: moxart: Include clk.h clk: cdce925: Include clk.h clk: Include clk.h in clk.c clk: zynq: Include clk.h clk: ti: Include clk.h clk: sunxi: Include clk.h and remove unused clkdev.h includes clk: st: Include clk.h clk: qcom: Include clk.h clk: highbank: Include clk.h clk: bcm: Include clk.h clk: versatile: Remove clk.h and clkdev.h includes clk: ux500: Remove clk.h and clkdev.h includes clk: tegra: Properly include clk.h ...
2015-07-28clk: mediatek: Add MT8173 MMPLL change rate supportJames Liao
MT8173 MMPLL frequency settings are different from common PLLs. It needs different post divider settings for some ranges of frequency. This patch add support for MT8173 MMPLL frequency setting by adding div-rate table to lookup suitable post divider setting under a specified frequency. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28clk: mediatek: Fix calculation of PLL rate settingsJames Liao
Avoid u32 overflow when calculate post divider setting, and increase the max post divider setting from 3 (/8) to 4 (/16). Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-28clk: mediatek: Fix PLL registers setting flowJames Liao
Write postdiv and pcw settings at the same time for PLLs if postdiv and pcw settings are on the same register. This is need by PLLs such as MT8173 MMPLL and ARM*PLL. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20clk: mediatek: Properly include clk.hStephen Boyd
We don't need to include clk.h in header files, just forward declare struct clk here. This leads us to a few places where the include of clk.h was missing in C files. Add them. Cc: James Liao <jamesjj.liao@mediatek.com> Cc: Henry Chen <henryc.chen@mediatek.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-06clk: mediatek: mt8173: Fix enabling of critical clocksSascha Hauer
On the MT8173 the clocks are provided by different units. To enable the critical clocks we must be sure that all parent clocks are already registered, otherwise the parents of the critical clocks end up being unused and get disabled later. To find a place where all parents are registered we try each time after we've registered some clocks if all known providers are present now and only then we enable the critical clocks Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> [sboyd@codeaurora.org: Marked function and data __init] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-06-04clk: mediatek: Fix apmixedsys clock registrationJames Liao
The size of clk_data should be the same as CLK_APMIXED_NR_CLK instead of ARRAY_SIZE(plls). CLK_APMIXED_* is numbered from 1, so CLK_APMIXED_NR_CLK will be greater than ARRAY_SIZE(plls). Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-20clk: mediatek: Initialize clk_init_dataRicky Liang
The variable init (struct clk_init_data) is allocated on the stack. We weren't initializing the .flags field, so it contains random junk, which can cause all kinds of interesting issues when the flags are parsed by clk_register. Signed-off-by: Ricky Liang <jcliang@chromium.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-06clk: mediatek: Add basic clocks for Mediatek MT8173.James Liao
This patch adds basic clocks for MT8173, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-06clk: mediatek: Add basic clocks for Mediatek MT8135.James Liao
This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs, INFRA and PERI clocks. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-06clk: mediatek: Add reset controller supportSascha Hauer
The pericfg and infracfg units also provide reset lines to several other SoC internal units. This adds a function which can be called from the pericfg and infracfg initialization functions which will register the reset controller using reset_controller_register. The reset controller will provide support for resetting the units connected to the pericfg and infracfg controller. The units resetted by this controller can use the standard reset device tree binding to gain access to the reset lines. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-05-06clk: mediatek: Add initial common clock support for Mediatek SoCs.James Liao
This patch adds common clock support for Mediatek SoCs, including plls, muxes and clock gates. Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> [sboyd@codeaurora.org: Squelch checkpatch warning in clk-mtk.h] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>