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path: root/drivers/dma/img-mdc-dma.c
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2015-12-18dmaengine: mdc: Correct terminate_all handlingDamien.Horsley
Use of the CANCEL bit in mdc_terminate_all creates an additional 'command done' to appear in the registers (in addition to an interrupt). In addition, there is a potential race between mdc_terminate_all and the irq handler if a transfer completes at the same time as the terminate all (presently this results in an inappropriate warning). To handle these issues, any outstanding 'command done' events are cleared during mdc_terminate_all and the irq handler takes no action when there are no new 'command done' events. Signed-off-by: Damien.Horsley <Damien.Horsley@imgtec.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-12-05dmaengine: img-mdc: Remove unnecessary synchronize_irq() before devm_free_irq()Lars-Peter Clausen
Calling synchronize_irq() right before devm_free_irq() is quite useless. On one hand the IRQ can easily fire again before devm_free_irq() is entered, on the other hand devm_free_irq() itself calls synchronize_irq() internally (in a race condition free way), before any state associated with the IRQ is freed. Patch was generated using the following semantic patch: // <smpl> @@ expression irq, dev; @@ -synchronize_irq(irq); devm_free_irq(dev, irq, ...); // </smpl> Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-03-18dmaengine: img-mdc: remove device_alloc_chan_resources handlerVinod Koul
Now that device_alloc_chan_resources handler in not mandatory, remove dummy implementations Acked-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2015-02-05dmaengine: Add driver for IMG MDCAndrew Bresticker
Add support for the IMG Multi-threaded DMA Controller (MDC) found on certain IMG SoCs. Currently this driver supports the variant present on the MIPS-based Pistachio SoC. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>