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path: root/drivers/pinctrl/pinctrl-tegra114.c
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2015-03-09pinctrl: tegra: some bits move between registersStephen Warren
Some of the pinmux configuration bits that exist in "drive group" registers in Tegra30..Tegra124 move to the "pinmux" registers on future chips. Add a flag to support this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-03-09pinctrl: tegra: driver layout/consistency fixesStephen Warren
Various non-semantic tweaks and layout/consistency fixes for existing Tegra pinctrl drivers. Move the definition of DRV_PINGROUP_REG() before the definition of PINGROUP() so that a future SoC driver can invoke the former from the latter. PINGROUP_BIT_Y(n) is just n, so replace it with n. Re-wrap the parameters to *PINGROUP(). Keep various enums sorted in the Tegra124 driver. Various white-space consistency fixes. These changes aim to update existing drivers to be consistent with future SoC drivers. While we could ignore these tweaks to the existing drivers, I'd like to keep everything as consistent as possible for easy comparison. Besides, I auto-generate the drivers, and maintaining special-cases to keep the differences in place is annoying. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-10-20pinctrl: drop owner assignment from platform_driversWolfram Sang
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-08-29pinctrl: Make of_device_id array constKiran Padwal
Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Kiran Padwal <kiran.padwal21@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: tegra: remove fsafe from data tablesStephen Warren
The fsafe value in the pingroup data tables is only used to implement tegra_pinctrl_disable(). The only reason this function is called is when dynamically switching between pinmux states, i.e. when disabling the old state before programming the new state. It's simpler to have the new target state define the expected value of each pin (and all current DTs do that). This also gives more flexibility, since it allows individual boards explicit control over the "inactive" mux function for each pin, rather than requiring it to be an SoC-specific value. Assuming this, we can get rid of the fsafe value from the driver completely, thus saving some more space in the driver tables. While re-writing the content of tegra124_pingroups[], fix the indentation to use a TAB instead of spaces. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-22pinctrl: tegra: remove redundant data table fieldsStephen Warren
Any SoC which supports the einput, odrain, lock, ioreset, or rcv_sel options has the relevant HW register fields in the same register as the mux function selection. Similarly, the drvtype option is always in the drive register, if it is supported at all. Hence, we don't need to have struct *_reg fields in the pin group table to define which register and bank to use for those options. Delete this to save space in the driver's data tables. However, many of those options are not supported on all SoCs, or not supported on some pingroups. We need a way to detect when they are supported. Previously, this was indicated by setting the struct *_reg field to -1. With the struct *_reg fields removed, we use the struct *_bit fields for this purpose instead. The struct *_bit fields need to be expanded from 5 to 6 bits in order to store a value outside the valid HW bit range of 0..31. Even without removing the struct *_reg fields, we still need to add code to validate the struct *_bit fields, since some struct *_bit fields were already being set to -1, without an option-specific struct *_reg field to "guard" them. In other words, before this change, the pinmux driver might allow some unsupported options to be written to HW. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-14pinctrl: tegra: add some missing Tegra114 entriesStephen Warren
Add some missing pin and drive group definitions to the driver. These are all defined in the TRM, but missing from the driver for some reason. Fix a couple of mistakes in the drive group definitions. Much of the diff to tegra114_groups[] is an indentation change due to one of the new group names being long. git diff/show -w will highlight this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12pinctrl: tegra: consistency cleanupStephen Warren
Fix Tegra30/114/124 pinmux drivers consistency issues. * Sort all lists of the same object type (e.g. #defines for pins, and the array that defines their names) in the same order. * Whitespace fixes. * Consistency in layout between the 3 drivers. These driver files were also auto-generated, which should allow us to make e.g. the U-Boot drivers completely consistent with the kernel in the future:-) Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-12pinctrl: tegra: dynamically calculate function list of groupsStephen Warren
The per-SoC data structures for Tegra pinctrl stored some information in a redundant way. Specifically, the list of groups that each function could be muxed onto was stored once explicitly, and also as part of the definition of each group. Eliminate this redundancy, and calculate each function's list of valid groups at pinctrl probe time. This removes thousands of lines of code from the pinctrl driver and ~16K from the vmlinux binary size, and adds only about 500uS to the boot process (on Tegra30; newer SoCs will likely be faster still). Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-03-11pinctrl: tegra: fix some typos and inconsistenciesStephen Warren
drive_dev3_pins in pinctrl-tegra114.c wasn't used; delete it. pinctrl-tegra124.c had quite a few typos. Fix those. pinctrl-tegra124.c had a few mismatches between the *_groups[] ararys and the function lists in tegra124_groups[]. Fix those. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-09-19pinctrl: tegra114: Remove MODULE_ALIASThierry Reding
The driver cannot be built as a module, so having a MODULE_ALIAS() isn't useful. While at it, fix a small typo in the file header comment and make the module description string consistent with those for earlier Tegra SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-02-15pinctrl: tegra: add clfvs function to Tegra114 supportRhyland Klein
This patch adds the definition for the cldvfs function for Tegra114 pinctrl support. This is based on work by Pritesh Raithatha. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2013-01-18pinctrl: tegra114: add pinctrl driver for NVIDIA's Tegra114 SoCPritesh Raithatha
This adds a driver for the Tegra114 pinmux, and required parameterization data for Tegra114. The driver uses the common Tegra pincontrol driver utility functions to implement the majority of the driver. This driver is not compatible with the earlier NVIDIA's SoCs, hence add new compatibile as "nvidia,tegra114-pinmux". Originally written by Pritesh. ldewangan: - cleanup the patches, - remove non-require tables. - Use module_platform_driver() for driver registartion. Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>