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2016-01-12Merge tag 'pinctrl-v4.5-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control patches for the v4.5 series. Notably I have a patch to driver core from Stephen Boyd in the pull request, this has been ACKed by Greg so it should be OK. The internal API needed some tweaking to allow modular Qualcomm pin controllers. There is a bit of development history in here but it should all add up nicely and has boiled in linux-next. For example I merged in v4.4-rc5 to get rid of some nasty merge conflicts. Summary: - New drivers: - PXA2xx pin controller support - Broadcom NSP pin controller support - New subdrivers: - Samsung EXYNOS5410 support - Qualcomm MSM8996 support - Qualcomm PM8994 support - Qualcomm PM8994 MPP support - Allwinner sunxi H3 support - Allwinner sunxi A80 support - Rockchip RK3228 support - Rename the Cygnus pinctrl driver to "iproc" as it is more generic than was originally thought. - A bunch of Lantiq/Xway updates especially from the OpenWRT people. - Several refactorings for the Super-H SH PFC pin controllers. Adding SCIF_CLK support. - Several fixes to the Atlas 7 driver. - Various fixes all over the place" * tag 'pinctrl-v4.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (91 commits) pinctrl: mediatek: Modify pinctrl bindings for mt2701 Revert "pinctrl: qcom: make PMIC drivers bool" pinctrl: qcom: Use platform_irq_count() instead of of_irq_count() driver-core: platform: Add platform_irq_count() pinctrl: lantiq: 2 pins have the wrong mux list pinctrl: qcom: make PMIC drivers bool pinctrl: nsp-gpio: forever loop in nsp_gpio_get_strength() pinctrl: mediatek: convert to arch_initcall pinctrl: bcm2835: Fix memory leak in error path pinctrl: mediatek: add missing of_node_put pinctrl: rockchip: add missing of_node_put pinctrl: sh-pfc: add missing of_node_put pinctrl: sirf: add missing of_node_put pinctrl-tegra: add missing of_node_put pinctrl: sunxi: Add A80 special pin controller pinctrl: bcm/cygnys/iproc: fixup rebase issue pinctrl: fixup problematic flag MAINTAINERS: Add co-maintainer for Renesas Pin Controllers pinctrl: sh-pfc: r8a7791: add EtherAVB pin groups pinctrl: sh-pfc: r8a7795: Add SATA support ...
2016-01-07Revert "pinctrl: qcom: make PMIC drivers bool"Stephen Boyd
This reverts commit bda7c4c2b9767ce2af4394754498662d62079af5. These drivers build as modules now that we use platform_irq_count() instead of of_irq_count(). Cc: Rob Herring <robh+dt@kernel.org> Cc: Andy Gross <andy.gross@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-07pinctrl: qcom: Use platform_irq_count() instead of of_irq_count()Stephen Boyd
of_irq_count() is not an exported symbol (and it shouldn't be used by platform drivers anyway) so use platform_irq_count() instead. This allows us to make the qcom pinctrl drivers modular again. Cc: Rob Herring <robh+dt@kernel.org> Cc: Andy Gross <andy.gross@linaro.org> Cc: Bjorn Andersson <bjorn@kryo.se> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2016-01-05pinctrl: lantiq: 2 pins have the wrong mux listJohn Crispin
The latest vendor SDK contained this patch. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-25pinctrl: qcom: make PMIC drivers boolLinus Walleij
commit ab4256cfeab91569e1d96e7f0014538fe0845259 "pinctrl: qcom: pmic-gpio/mpp: of_irq_count() == npins" made the Qualcomm PMIC pin control drivers make use of of_irq_count() which is not an exported function, making modular builds fail. Fix this by marking the drivers as compiled-in/bool. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Andy Gross <andy.gross@linaro.org> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-24pinctrl: nsp-gpio: forever loop in nsp_gpio_get_strength()Dan Carpenter
There is a signedness bug here so the loop will never exit. Fixes: 8bfcbbbcabe0 ('pinctrl: nsp: add gpio-a driver support for Broadcom NSP SoC') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-24Merge tag 'samsung-drivers-4.5' of ↵Linus Walleij
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into devel Exynos-specific drivers for 4.5: 1. Add a pinctrl driver for Exynos5410.
2015-12-22pinctrl: mediatek: convert to arch_initcallDaniel Kurtz
Move pinctrl initialization earlier in boot so that real devices can find their pctldev without probe deferring. Note: We don't change mt6397 probe order in this patch, since MT6397 is mfd PMIC, which depends on pwrap on main AP to work. Since pmic-wrap itself is module_platform_driver, we keep it as module_init. A later patch will convert both pmic-wrap, and all functions of the MT6397 mfd to arch_initcall. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl: bcm2835: Fix memory leak in error pathStefan Wahren
In case of an invalid pin value bcm2835_pctl_dt_node_to_map() would leak the pull configs of already assigned pins. So avoid this by calling the free map function in error case. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Fixes: e1b2dc70cd5b ("pinctrl: add bcm2835 driver") Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl: mediatek: add missing of_node_putJulia Lawall
for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl: rockchip: add missing of_node_putJulia Lawall
for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl: sh-pfc: add missing of_node_putJulia Lawall
for_each_child_of_node performs an of_node_get on each iteration, so a goto out of the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e,e1; identifier l; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? goto l; ) ... } l: ... when != n // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl: sirf: add missing of_node_putJulia Lawall
for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl-tegra: add missing of_node_putJulia Lawall
for_each_child_of_node performs an of_node_get on each iteration, so a return from the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ local idexpression n; expression e,e1; @@ for_each_child_of_node(e1,n) { ... ( of_node_put(n); | e = n | return n; | + of_node_put(n); ? return ...; ) ... } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22pinctrl: sunxi: Add A80 special pin controllerMaxime Ripard
Like the previous designs, the A80 has a special pin controller for the critical pins, like the PMIC bus. Add a driver for this controller. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [wens: Add A80 compatible strings to bindings doc; fix pin function names based on v1.3 datasheet; constify of_device_id table] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-22Merge branch 'sh-pfc-for-v4.5' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
2015-12-21pinctrl: bcm/cygnys/iproc: fixup rebase issueLinus Walleij
Somehow this variable name screwed up in some rebase, fixed it. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reported-by: Pramod Kumar <pramodku@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-17Merge tag 'v4.4-rc5' into develLinus Walleij
Linux 4.4-rc5
2015-12-17pinctrl: fixup problematic flagLinus Walleij
This removes the set_irq_flags() call that unfortunately slipped into the BCM NSP driver. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Yendapally Reddy Dhananjaya Reddy <yrdreddy@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-16pinctrl: sh-pfc: r8a7791: add EtherAVB pin groupsSergei Shtylyov
Add the EtherAVB pin groups to the R8A7791 PFC driver. Also add the copyright for all the Cogent Embedded's past work on this file. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-12-16pinctrl: sh-pfc: r8a7795: Add SATA supportTakeshi Kihara
This patch adds SATA0 pinmux support to r8a7795 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> [uli: adjusted for new PFC driver] Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-12-16pinctrl: sh-pfc: r8a7795: Add SDHI supportTakeshi Kihara
Add SDHI[0-3] pinmux support to r8a7795 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-12-16pinctrl: sh-pfc: r8a7794: Add SCIF_CLK supportGeert Uytterhoeven
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-16pinctrl: sh-pfc: r8a7790: Add SCIF_CLK supportGeert Uytterhoeven
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-16pinctrl: sh-pfc: r8a7779: Add SCIF_CLK supportGeert Uytterhoeven
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on SCIF. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-15pinctrl: pxa: pxa2xx: add pin control skeletonRobert Jarzmik
The wrong free functions were used to release temporary buffers. This didn't show up in the normal driver's life. Yet in suspend to RAM, the managed resource list is walked, and as memory was released, the list is corrupted and make the kernel Oops. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-14pinctrl: bcm2835: Fix initial value for direction_outputStefan Wahren
Currently the provided initial value for bcm2835_gpio_direction_output has no effect. So fix this issue by changing the value before changing the GPIO direction. As a result we need to move the function below bcm2835_gpio_set. Suggested-by: Martin Sperl <kernel@martin.sperl.org> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Fixes: e1b2dc70cd5b ("pinctrl: add bcm2835 driver") Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-11pinctrl: rockchip: add support for the rk3228Jeffy Chen
The pinctrl of rk3228 is much the same as rk3288's, but without pmu. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-11pinctrl: sunxi: Add H3 PIO controller supportJens Kuske
The H3 uses the same pin controller as previous SoC's from Allwinner. Add support for the pins controlled by the main PIO controller. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: bcm: Default PINCTRL_BCM281XX to y for ARCH_BCM_MOBILEFlorian Fainelli
This driver is mandatory for proper operation on the platforms covered by the ARCH_BCM_MOBILE Kconfig symbol, make sure we do that driver on for these platforms. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: at91: Use platform_register/unregister_drivers()Thierry Reding
These new helpers simplify implementing multi-driver modules and properly handle failure to register one driver by unregistering all previously registered drivers. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: adi2: Use platform_register/unregister_drivers()Thierry Reding
These new helpers simplify implementing multi-driver modules and properly handle failure to register one driver by unregistering all previously registered drivers. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10Revert "pinctrl: intel: fix bug of register offset calculation"Linus Walleij
This reverts commit c5cdcba3d54b9bd2443bd0afe9f4828f802a944f.
2015-12-10pinctrl: intel: fix offset calculation issue of register PAD_OWNQipeng Zha
The calculation equation of PAD_OWN register offset is not correct for Broxton, verified this fix will get right offset for Broxton. Signed-off-by: Qi Zheng <qi.zheng@intel.com> Signed-off-by: Qipeng Zha <qipeng.zha@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: intel: fix bug of register offset calculationQipeng Zha
The group size for registers PADCFGLOCK, HOSTSW_OWN, GPI_IS, GPI_IE, are not 24 for Broxton, Add a parameter to allow different platform to set correct value. Signed-off-by: Qi Zheng <qi.zheng@intel.com> Signed-off-by: Qipeng Zha <qipeng.zha@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10Merge branch 'bcm-nsp' into develLinus Walleij
2015-12-10pinctrl: nsp: add gpio-a driver support for Broadcom NSP SoCYendapally Reddy Dhananjaya Reddy
This adds the initial support of the Broadcom NSP gpio-a driver. Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yrdreddy@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: at91-pio4: fix memleak after using dt mapLudovic Desroches
configs is allocated by pinconf_generic_parse_dt_config(), pinctrl_utils_add_map_configs() duplicates configs so it can and has to be freed to prevent memory leaks. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Reported-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: freescale: add ZERO_OFFSET_VALID flag for vf610 pinctrlShawn Guo
To support i.MX7D Low Power State Retention IOMUXC, commit e7b37a522aa9 ("pinctrl: freescale: imx: allow mux_reg offset zero") changes the way of zero mux_reg offset support with a new flag ZERO_OFFSET_VALID. But, unfortunately, it forgot to add this flag for vf610 pinctrl which has zero mux_reg offset be valid as well, and hence breaks the vf610 support. Fix the regression by adding flag ZERO_OFFSET_VALID for vf610 pinctrl driver. Signed-off-by: Shawn Guo <shawnguo@kernel.org> Fixes: e7b37a522aa9 ("pinctrl: freescale: imx: allow mux_reg offset zero") Reported-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: atlas7: add pulse conter pin group without direction pinGuoying Zhang
DR needs use the pulse counter direction pin as common gpio function. Signed-off-by: Guoying Zhang <Guoying.Zhang@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: atlas7: adjust vip pin groups for atlas7Wei Chen
The vip low 8bit mode and vip high 8 bit mode pin groups had missed 3 pins:vip_vsync, vip_hsync and vip_pxclk. Without these 3 pins, the vip could not work properly. Now we add these 3 pins into these two pin groups. Signed-off-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: atlas7: adjust pin groups of atlas7 nanddiskWei Chen
Remove write-protect and chip-selector pins from nand pin group. And then create two separate pin groups for these two pin. So the nand driver can choose correct pin groups as board desgin: For example: 1. nand without wp&cs: nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx>; }; 2. nand with wp nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx &nd_df_wp_pmx>; }; 3. nand with cs: nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx &nd_df_cs_pmx>; }; 4. nand with wp&cs: nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx &nd_df_wp_pmx &nd_df_cs_pmx>; }; Signed-off-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: altas7: add sd9 function mux supportYonghui Zhang
The sd9 pin mux with sd3 and it is selected by SYS2PCI_SDIO9SEL. This makes the codes ugly since the register is not in pinctrl module. Signed-off-by: Yonghui Zhang <yonghui.zhang@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: atlas7: add cs line for atlas7 nandWei Chen
The nand in atlas7 has two chip select line. But in most time, the nand only has one chip, so only one chip select line is enough. The nand driver select this new pin group can free one chip select line for other modules to avoid pin conflict. Signed-off-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: activate pxa architectureRobert Jarzmik
As the pxa architecture, at least for pxa27x, supports pin control, activate it in the pinctrl tree. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: pxa: add pxa27x architectureRobert Jarzmik
Add the pxa27x architecture, which is a pxa2xx with 128 pins. The registers spacing, and pins logic is common to pxa2xx, only the pins and their alternate function are specific to pxa27x. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: pxa: pxa2xx: add pin configuration supportRobert Jarzmik
Add pin configuration for pxa2xx architectures. PXA doesn't provide any bias, push, pull capabilities. The only capability is to set a state for the pins when the platform enter sleep or deep sleep mode. The state of a pin is set by : - whether the GPIO direction was input or output - if it is output, a register set programs whether the pin should be held to ground or VccIO Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: pxa: pxa2xx: add pin muxingRobert Jarzmik
The driver is inspired from the sunxi driver. The pxa architecture specificities leading to the driver are : - each pin has 8 possible alternate functions - 4 of these are output kind - 4 of these are input kind - there is always a "gpio input" and "gpio output" function - the function matrix is very scattered : - some functions can be found on 5 different pads - the number of functions is greater than the number of pins - there is no "topology" grouping of pins (such as all SPI in one corner of the die) Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10pinctrl: pxa: pxa2xx: add pin control skeletonRobert Jarzmik
Add a pincontrol driver for pxa2xx architecture, encompassing all pxa25x and pxa27x variants. This is only the pin muxing part of the driver. One specific consideration is also the memory space (MMIO), which is intertwined with the GPIO registers. To make things worse, the GPIO direction register also affect pin muxing, as it chooses the "kind" of pin, ie. the 4 output functions or 4 input functions. The mapping between pinctrl notions and PXA Technical Reference Manual is as follows : - a pin is obviously a pin - a group is also a pin, ie. group P101 is the pin 101 - a mux function is an alternate function (ie. gpio-in, gpio-out, MMCLK, BTRTS, etc ...) The individual architecture (pxa27x, pxa25x) instantiate a pin control by providing a table of pins, each pin being provided a list of PXA_FUNCTION (alternate functions). Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2015-12-10Merge branch 'sh-pfc-for-v4.5' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
generated by cgit v0.10.2 at 2024-10-08 18:44:23 (GMT)