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'spi/topic/pxa2xx' and 'spi/topic/qup' into spi-next
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'spi/topic/jcore', 'spi/topic/loopback' and 'spi/topic/meson' into spi-next
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This spi driver uses the common spi-bcm-qspi driver and implements iProc
SoCs specific interrupt controller. The common driver now calls the SoC
handlers when present. Adding support for both muxed l1 and unmuxed interrupt
sources.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Adding the settop SoC platfrom driver, this driver is compatible
with the settop MSPI+BSPI and MSPI only blocks implemented on the
SoCs. Driver calls the spi-bcm-qspi probe(), remove() and pm_ops.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Master SPI driver for Broadcom settop, iProc SoCs. The driver
is used for devices that use SPI protocol on BRCMSTB, NSP, NS2
SoCs. SoC platform driver call exported porbe(), remove()
and suspend/resume pm_ops implemented in this common driver.
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Yendapally Reddy Dhananjaya Reddy
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add ThunderX SPI driver using the shared part from the Octeon
driver. The main difference of the ThunderX driver is that it
is a PCI device so probing is different. The system clock settings
can be specified in device tree.
Signed-off-by: Jan Glauber <jglauber@cavium.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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The J-Core "spi2" device is a PIO-based SPI master controller. It
differs from "bitbang" devices in that that it's clocked in hardware
rather than via soft clock modulation over gpio, and performs
byte-at-a-time transfers between the cpu and SPI controller.
This driver will be extended to support future versions of the J-Core
SPI controller with DMA transfers when they become available.
Signed-off-by: Rich Felker <dalias@libc.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Separate driver probing from SPI transfer functions.
Signed-off-by: Jan Glauber <jglauber@cavium.com>
Tested-by: Steven J. Hill <steven.hill@cavium.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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This driver implements SPI master interface for Quad SPI
controller, specifically for accessing quad SPI flash.
It uses descriptor-based DMA transfer mode and supports
half-duplex communication for single, dual and quad SPI
transactions.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
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The PIC32 SPI driver is capable of performing SPI transfers
using PIO or external DMA engine. GPIO controlled /CS support
is made default in the driver for correct operation of the
controller. This can be enabled by adding "cs-gpios" property
of the SPI node in board dts file.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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'spi/topic/pl022' and 'spi/topic/pxa2xx' into spi-next
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ICP DAS LP-8841 contains a DS-1302 RTC. This driver provides an SPI
master which makes the RTC usable. The driver is not supposed to work
with anything else.
The driver uses the standard MicroWire half-duplex transfer timing.
Master output is set on low clock and sensed by the RTC on the rising
edge. Master input is set by the RTC on the trailing edge and is sensed
by the master on low clock.
Signed-off-by: Sergei Ianovich <ynvich@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi into spi-pxa2xx
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This patch adds support for the AXI SPI Engine controller which is a FPGA
soft-peripheral which is used in some of Analog Devices' reference designs.
The AXI SPI Engine controller is part of the SPI Engine framework[1] and
allows memory mapped access to the SPI Engine control bus. This allows it
to be used as a general purpose software driven SPI controller. The SPI
Engine in addition offers some optional advanced acceleration and
offloading capabilities, which are not part of this patch though and will
be introduced separately.
At the core of the SPI Engine framework is a small sort of co-processor
that accepts a command stream and turns the commands into low-level SPI
transactions. Communication is done through three memory mapped FIFOs in
the register map of the AXI SPI Engine peripheral. One FIFO for the command
stream and one each for transmit and receive data.
The driver translates a spi_message in a command stream and writes it to
the peripheral which executes it asynchronously. This allows it to perform
very precise timings which are required for some SPI slave devices to
achieve maximum performance (e.g. analog-to-digital and digital-to-analog
converters). The execution flow is synchronized to the host system by a
special synchronize instruction which generates a interrupt.
[1] https://wiki.analog.com/resources/fpga/peripherals/spi_engine
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
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After removal of legacy PXA DMA code by the commit 6356437e65c2
("spi: spi-pxa2xx: remove legacy PXA DMA bits") the
CONFIG_SPI_PXA2XX_DMA follows the CONFIG_SPI_PXA2XX and cannot be disabled
alone. Therefore remove this config symbol and dead definitions from the
spi-pxa2xx.h.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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adding the spi-loopback-test module to Kconfig and Makefile
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
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The bcm2835 has 2 auxiliary spi bus masters spi1 and spi2.
This implements the driver to enable these devices.
The driver does not implement native chip-selects but uses
the aribtrary GPIO-chip-selects provided by the spi-chipselect.
Note that this driver relies on the fact that
the clock is implemented by the clk-bcm2835-aux driver,
which enables/disables the HW block when requesting/releasing
the clock.
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
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'spi/topic/xlp' into spi-next
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Add SPI Master controller driver for the SPI interface on XLP8XX,
XLP3XX, XLP2XX, XLP9XX and XLP5XX family of Netlogic XLP MIPS64 processors.
Signed-off-by: Kamlakant Patel <kamlakant.patel@broadcom.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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This patch adds basic spi bus for MT8173.
Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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'spi/topic/zynq' into spi-next
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'spi/topic/rspi', 'spi/topic/s3c64xx' and 'spi/topic/sh-msiof' into spi-next
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This patch adds support for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode <ranjit.waghmode@xilinx.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Generic DMA support was already implemented by commit cd7bed003404
("spi/pxa2xx: break out the private DMA API usage into a separate file")
which moved all the legacy PXA DMA implementation code into its own
file.
With generic DMA available for PXA, we can now just trash this file.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Mark Brown <broonie@linaro.org>
[respin after pxa dmaengine support upstream]
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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This driver mediates access between the connected CPLD and other devices
on the bus.
The m25p80-compatible boot flash and (some models) MMC use regular SPI,
bitbanged as required by the SoC. However the SPI-connected CPLD has
a two-wire mode, in which two bits are transferred per SPI clock
cycle. The second bit is transmitted with the SoC's CS2 pin.
Signed-off-by: Bert Vermeulen <bert@biot.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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'spi/topic/st-ssc' and 'spi/topic/ti-qspi' into spi-next
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This adds support for Diolan DLN2 USB-SPI adapter.
Information about the USB protocol interface can be found in the
Programmer's Reference Manual [1], see section 5.4.6 for the SPI
master module commands and responses.
[1] https://www.diolan.com/downloads/dln-api-manual.pdf
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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This patch adds support for the SPI portion of ST's SSC device.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
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'spi/topic/gpio', 'spi/topic/img-spfi' and 'spi/topic/meson' into spi-next
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This is a driver for the Amlogic Meson SPIFC (SPI flash controller),
which is one of the two SPI controllers available on the SoC. It
doesn't support DMA and has a 64-byte unified transmit/receive buffer.
The device is optimized for interfacing with SPI NOR memories and
allows the execution of standard operations such as read, page
program, sector erase, etc. in a simplified way, toggling a bit in a
dedicated register. The driver doesn't use those predefined commands
and relies only on custom transfers.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add support for the Synchronous Peripheral Flash Interface (SPFI) master
controller found on IMG SoCs. The SPFI controller supports 5 chip-select
lines and single/dual/quad mode SPI transfers.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
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Broadcom 53xx ARM SoCs use bcma bus that contains various cores (AKA
devices). If board has a serial flash, it's connected over SPI and the
bcma bus includes a SPI controller. Example log from such a board:
bus0: Found chip with id 53010, rev 0x00 and package 0x02
(...)
bus0: Core 18 found: SPI flash controller (manuf 0x4BF, id 0x50A, rev 0x01, class 0x0)
This patch adds a bcma driver for SPI core, it registers SPI master
controller and "bcm53xxspiflash" SPI device.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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In order to facilitate understanding, rockchip SPI controller IP design
looks similar in its registers to designware. But IC implementation
is different from designware, So we need a dedicated driver for Rockchip
RK3XXX SoCs integrated SPI. The main differences:
- dma request line: rockchip SPI controller have two DMA request line
for tx and rx.
- Register offset:
RK3288 dw
SPI_CTRLR0 0x0000 0x0000
SPI_CTRLR1 0x0004 0x0004
SPI_SSIENR 0x0008 0x0008
SPI_MWCR NONE 0x000c
SPI_SER 0x000c 0x0010
SPI_BAUDR 0x0010 0x0014
SPI_TXFTLR 0x0014 0x0018
SPI_RXFTLR 0x0018 0x001c
SPI_TXFLR 0x001c 0x0020
SPI_RXFLR 0x0020 0x0024
SPI_SR 0x0024 0x0028
SPI_IPR 0x0028 NONE
SPI_IMR 0x002c 0x002c
SPI_ISR 0x0030 0x0030
SPI_RISR 0x0034 0x0034
SPI_TXOICR NONE 0x0038
SPI_RXOICR NONE 0x003c
SPI_RXUICR NONE 0x0040
SPI_MSTICR NONE 0x0044
SPI_ICR 0x0038 0x0048
SPI_DMACR 0x003c 0x004c
SPI_DMATDLR 0x0040 0x0050
SPI_DMARDLR 0x0044 0x0054
SPI_TXDR 0x0400 NONE
SPI_RXDR 0x0800 NONE
SPI_IDR NONE 0x0058
SPI_VERSION NONE 0x005c
SPI_DR NONE 0x0060
- register configuration:
such as SPI_CTRLRO in rockchip SPI controller:
cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
| (CR0_SSD_ONE << CR0_SSD_OFFSET);
cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
cr0 |= (rs->tmode << CR0_XFM_OFFSET);
cr0 |= (rs->type << CR0_FRF_OFFSET);
For more information, see RK3288 chip manual.
- Wait for idle: Must ensure that the FIFO data has been sent out
before the next transfer.
Signed-off-by: addy ke <addy.ke@rock-chips.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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'spi/topic/cadence' into spi-next
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Add driver for Cadence SPI controller. This is used in Xilinx Zynq.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Spi v3 controller is not only used on Blackfin. So rename it
and use ioread/iowrite api to make it work on other platform.
Signed-off-by: Scott Jiang <scott.jiang.linux@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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into spi-next
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'spi/topic/ti-qspi', 'spi/topic/ti-ssp', 'spi/topic/topcliff-pch', 'spi/topic/txx9', 'spi/topic/xcomm' and 'spi/topic/xfer' into spi-next
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The tnetv107x platform is getting removed, so this driver
will not be needed any more.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Acked-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
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This simple SPI master controller is built into xtfpga bitstreams. It
always transfers 16 bit words in SPI mode 0, automatically asserting CS
on transfer start and deasserting on end.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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The older Allwinner SoCs (A10, A13, A10s and A20) all have the same SPI
controller.
Unfortunately, this SPI controller, even though quite similar, is significantly
different from the recently supported A31 SPI controller (different registers
offset, split/merged registers, etc.). Supporting both controllers in a single
driver would be unreasonable, hence the addition of a new driver.
Like its more recent counterpart, it supports DMA, but the driver only does PIO
until we have a dmaengine driver for this platform.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Qualcomm Universal Peripheral (QUP) core is an AHB slave that
provides a common data path (an output FIFO and an input FIFO)
for serial peripheral interface (SPI) mini-core. SPI in master
mode supports up to 50MHz, up to four chip selects, programmable
data path from 4 bits to 32 bits and numerous protocol variants.
Cc: Alok Chauhan <alokc@codeaurora.org>
Cc: Gilad Avidov <gavidov@codeaurora.org>
Cc: Kiran Gunda <kgunda@codeaurora.org>
Cc: Sagar Dharia <sdharia@codeaurora.org>
Cc: dsneddon@codeaurora.org
Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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The Allwinner A31 has a new SPI controller IP compared to the older Allwinner
SoCs.
It supports DMA, but the driver only does PIO for now, and DMA will be
supported eventually.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Add a driver for the High Speed SPI controller found on newer BCM63XX SoCs.
It does feature some new modes like 3-wire or dual spi, but neither of it
is currently implemented.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
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The patch add basic support for the quad spi controller.
QSPI is a kind of spi module that allows single,
dual and quad read access to external spi devices. The module
has a memory mapped interface which provide direct interface
for accessing data form external spi devices.
The patch will configure controller clocks, device control
register and for defining low level transfer apis which
will be used by the spi framework to transfer data to
the slave spi device(flash in this case).
Test details:
-------------
Tested this on dra7 board.
Test1: Ran mtd_stesstest for 40000 iterations.
- All iterations went through without failure.
Test2: Use mtd utilities:
- flash_erase to erase the flash device
- mtd_debug read to read data back.
- mtd_debug write to write to the data flash.
diff between the write and read data shows zero.
Acked-by: Felipe Balbi<balbi@ti.com>
Reviewed-by: Felipe Balbi<balbi@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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The serial peripheral interface (SPI) module implemented on Freescale Vybrid
platform provides a synchronous serial bus for communication between Vybrid
and the external peripheral device.
The SPI supports full-duplex, three-wire synchronous transfer, has TX/RX FIFO
with depth of four entries.
This driver is the SPI master mode driver and has been tested on Vybrid
VF610TWR board.
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Chao Fu <b44548@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
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